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14282:1a6b51a56fa5 |
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05-Sep-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: PSTATE.PAN changes should inval cached regs in TLB
Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14228:8c1143372c76 |
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20-Aug-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs
The readMiscReg/setMiscReg methods were not forwarding register reads/writes to the cpu interface when in AArch32.
Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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14133:f3e7e7c3803d |
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06-Aug-2019 |
Jordi Vaquero <jordi.vaquero@metempsy.com> |
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system.
Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14128:6ed23d07d0d1 |
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28-Jul-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Implement ARMv8.1-PAN, Privileged access never
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state bit is 1, any privileged data access from EL1 or EL2 to a virtual memory address that is accessible at EL0 generates a Permission fault. This feature is mandatory in ARMv8.1 implementations. This feature is supported in AArch64 and AArch32 states. The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields identify the support for ARMv8.1-PAN.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: I94a76311711739dd2394c72944d88ba9321fd159 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14000:d85c61dc0b5c |
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19-Feb-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Expose haveGicv3CPUInterface to the ISA interface
Change-Id: I36232b7618ad875983f34b741c51f12ddb9ae166 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17989 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13882:03fe9a85b435 |
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10-Apr-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Remove un-needed hyp flag in TLBI operations
The hyp flag was probably a legacy pre-v8 flag distinguishing invalidation targeting PL2 translation regime (hyp mode). Since the introduction of target_el parameter, hyp boolean is not needed anymore. The patch works by setting the hyp flag in the flush* methods in the TLB automatically by checking if target_el == EL2.
Change-Id: I798009e09ff24a383dea871e348188bae2685e8e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18389 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13881:955558193370 |
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10-Apr-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Correct target EL field in TLBI operations
Some TLB Invalidation operations affecting the EL2 translation regime were marked as targeting EL1 instead of EL2
Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18388 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13826:34a9929c35eb |
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18-Feb-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13759:9941fca869a9 |
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16-Oct-2018 |
Giacomo Gabrielli <giacomo.gabrielli@arm.com> |
arch-arm,cpu: Add initial support for Arm SVE
This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support.
Additional authors: - Javier Setoain <javier.setoain@arm.com> - Gabor Dozsa <gabor.dozsa@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com>
Thanks to Pau Cabre for his contribution of bugfixes.
Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13691:9c9a28fdb97f |
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29-Jan-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Move GICv3 detection at startup time
At the moment the haveGicV3 parameter is used only to signal its presence when reading the MISCREG_ID_AA64PFR0_EL1 register. It depends on the system->getGIC pointing to a GICv3 model. However this pointer is set in the System only at init time (after construction), which means that the haveGICv3CPUInterface will always be false. This patch is fixing this by moving the parameter initialization at startup time, together with the cpu interface registration.
Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16483 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13599:05e9234fef20 |
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09-Jan-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Inital vector rename mode depending on A32/A64
Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481 Reviewed-on: https://gem5-review.googlesource.com/c/15599 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13582:989577bf6abc |
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18-Oct-2018 |
Gabe Black <gabeblack@google.com> |
arch: cpu: Stop passing around misc registers by reference.
These values are all basic integers (specifically uint64_t now), and so passing them by const & is actually less efficient since there's a extra level of indirection and an extra value, and the same sized value (a 64 bit pointer vs. a 64 bit int) is being passed around.
Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3 Reviewed-on: https://gem5-review.googlesource.com/c/13626 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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13581:b6dcd0183747 |
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13-Oct-2018 |
Gabe Black <gabeblack@google.com> |
arm: Get rid of some register type definitions.
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal.
Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435 Reviewed-on: https://gem5-review.googlesource.com/c/13625 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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13550:976591c112bc |
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18-Dec-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled
Trying to read MPIDR(_EL1) from EL1, should return the value of VMPIDR_EL2 if EL2 is enabled. This patch is modifying the utility function for reading MPIDR in order to match this behaviour for both AArch32 and AArch64.
Change-Id: I32c2d4d5052f509e6e0542a5314844164221c6a3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15617 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13549:307ffddbd819 |
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02-Sep-2018 |
Anouk Van Laer <anouk.vanlaer@arm.com> |
arch-arm: Added TLBI_ALL EL2 instruction
This patch is adding TLBI_ALLE2(IS) operations to the arm ISA.
Change-Id: I8e35cff9a2cc414f4c5fbbc5aa0cfe5023a3f011 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15616 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13531:e6f1bf55d038 |
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11-Oct-2018 |
Jairo Balart <jairo.balart@metempsy.com> |
dev-arm: Add a GICv3 model
Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1 Reviewed-on: https://gem5-review.googlesource.com/c/13436 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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13502:7803bd430e0e |
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07-May-2018 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: properly handle RES0/1 for SCTLRs
They were being treated as RAZ/RAO, which is incorrect. Put the access masks in the register metadatabase now that we have one.
Also fix this for HVBAR.
Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/10401 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13499:7f9d435bac22 |
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20-Sep-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Add Crypto in SE mode
This patch is also enabling AArch32 crypto instructions by setting the ID_ISAR5 register accordingly.
Change-Id: Id412585b39b78570a65bd3047199c84e9db76cda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15155 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13417:d5030340d89a |
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12-Nov-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Print register name when warning on AT instructions
With this patch we don't print anymore the enum value when warning on any AT instruction usage, but we print the sys reg name instead
Change-Id: Ic6831b98ad6b0582be69883dc9519a9d3324da30 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14316 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13396:23277eaae855 |
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31-Oct-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32
ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed.
At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address.
Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13393:659fdbcd5722 |
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31-Oct-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Refactor ISA::clear by adding a ISA::clear32 method
The patch is also moving some initialization code to be used by AArch64 as well since the registers are mapped to AArch64 ones.
Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13997 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13173:210b6fc57533 |
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17-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Add have_crypto System parameter
This patch adds the have_crypto ArmSystem parameter for enabling crypto extension. This is done by modifying the AArch32/AArch64 ID registers at startup time.
Change-Id: I6eefb7e6f6354802a14ea639ad53b75f8e1e11c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13252 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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13116:d3c3e2533928 |
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25-Sep-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
This patch implements AArch64 Memory Model Feature Register 2 (from ARMv8.2)
Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13066 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13114:777d445423d6 |
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24-Sep-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Init AArch64 ID registers in SE mode
One of the auxv vector's flag is the HWCAP, whose bits match the content of several arm ID registers. This patch factors out AArch64 ID registers init into a separate method and creates the symmetric AArch32 ID register init as well, so that we get a meaningful auxiliary vector in SE mode.
Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13064 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12972:832a2d71a6cf |
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23-Mar-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm: Add support for tracking TCs in ISA devices
ISA devices typically need to keep track of the thread context they are associated with. Among other things, this is required for interrupt delivery. Add a BaseISADevice:setThreadContext() method to wire such models to the right thread context.
Change-Id: Iad354d176c0c4c4e34c6ab8b5acaee0b69da0406 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12399 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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12816:9e9bd9e6e206 |
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17-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers into the decode tree. They are currently implemented as a generic timer and produces a warning if accessed.
Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12763:37c243ed1112 |
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29-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Add Illegal Execution flag to PCState
This patch moves the detection of the Illegal Execution flag (PSTATE.IL) from the tlb translation stage (fetch) to the decoding stage. This is done by adding the illegalExecution field to the PCState.
Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12749:223c83ed9979 |
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04-Jun-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12714:6870e0c151b1 |
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09-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail.
Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12690:810dd3bdac8f |
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25-Apr-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Map ID_x_EL1 registers to AArch32 version
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those registers must be initialized even when the highest Exception Level is using AArch64.
Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12675:f3439303feb4 |
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17-Apr-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Add ARMv8.1 TTBR1_EL2 register
This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception)
Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12671:2a9f13f15e91 |
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17-Jan-2018 |
Chuan Zhu <chuan.zhu@arm.com> |
arch-arm: Fix masking in CPACR_EL1
Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit CPACR_EL1[31] is RES0 but should be made stateful, since it allows programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1 is removed.
Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10046 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12670:d662ee5a095a |
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29-Dec-2017 |
Chuan Zhu <chuan.zhu@arm.com> |
arch-arm: Mask out unsupported trapped exception handling bits
Floating-point trapped exception handlings are not currently supported in gem5, therefore the corresponding bits are RAZ/WI in FCPR.
Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10045 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12667:1b939161dcb8 |
|
15-Jan-2018 |
Chuan Zhu <chuan.zhu@arm.com> |
arch-arm: Correct masking of cp10 and cp11 in CPACR
This patch fixes the masking of cp10 and cp11 in CPACR according to NSACR.cp10 / NSACR.cp11 by adding the condition "in Non-secure state, if EL3 is implemented and is using AArch32...", which is specified in ARM ARM.
Change-Id: Id00e7bf04d6a985e27dbf1028677da0746b79924 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10044 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12666:bea22b5e6cf7 |
|
11-Dec-2017 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Using explicit invalidation in TLB
When setting TLB related MiscRegs, using explicit TLB regs invalidation rather than implicit switch-case fallthrough
Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10041 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
#
12639:c133e5b397a4 |
|
27-Mar-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Fix secure write of SCTLR when EL3 is AArch64
MiscRegisters are not banked between secure and non-secure mode if EL3 is not implemented or if EL3 is using AArch64 (highestELIs64). In this scenario a unique register is used and it is mapped to the NS version (see snsBankedIndex implementation), so that a secure world read/write should access the non secure storage.
Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
#
12605:16476b32138d |
|
22-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Distinguish IS TLBI from non-IS
TLBI broadcasting was the default implementation of most of TLBI instructions. This patch applies the broadcasting behaviour only to the Inner-Shareable subset, while simpler TLB invalidation instructions only affect the PE that executes them.
Change-Id: Idb01d0d4f593131f657e8fc9668112de8e4ccdcb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9182 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12604:0cf3d5d3bd3e |
|
22-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Created function for TLB ASID Invalidation
This patch is intended to avoid code duplication and extends the set of TLBI ISA functions adding the entry invalidation by ASID match.
Change-Id: I9bcb498059ea480dd2118639c7b3c64fea80a5e1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9181 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12577:5cafe57f87e5 |
|
24-Jan-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Adding IPA-Based Invalidating instructions
This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L.
Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
#
12576:e55d2103ccac |
|
23-Jan-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Implement missing aarch32 TLBI registers
In the pool of TLB Invalidate system register a category of instruction was missing: the ones operating on entries added to the TLB during the last level only of a table walk. (E.g. TLBIVMAL). This patch is not considering this matching criteria when invalidating the entries and it is rather performing the invalidation on all levels.
Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
#
12570:e32771e88250 |
|
09-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Fix FSC generation in AbortFault
The fault status code generated by a Prefetch/Data Fault was containing a wrong value when the fault was triggered in aarch32 but handled in aarch64. This because the encoding differs between the two ISAs and the encoder was just checking the starting ISA rather than the the ending one. In this case the getFsr must be called after we know which is the ending ISA, which happens only after ArmFault::invoke gets called. The fsc update hence happens before writing into the Syndrome register.
Change-Id: I725f12b6dcc0178f608233bd3d15e466d1cd1ffc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8362 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12524:723cf62f5a46 |
|
09-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Change ArmFault cast from reinterpret to static
Changing casting type in src/arch/arm/isa.cc
Change-Id: Ia19b30a1bf8b1b25df149b52613a3533eaced03a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8241 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12510:b8203d3676fc |
|
19-Dec-2017 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Don't change PSTATE in Illegal Exception return
This patch fixes the Illegal Exception return handler. According to the armarm documentation, when PSTATE.IL is set to one because of an illegal exception return, PSTATE.{EL, nRW, SP} are unchanged. This means the Exception level, Execution state, and stack pointer selection do not change as a result of the return.
Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8021 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12479:c686e4a1fe8f |
|
06-Dec-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arch-arm: understandably initialize register permissions
Move massive initialization routine to the bottom of miscregs.cc. Additionally, share register metadata across ISA instances by making lookUpMiscReg a static member of the ISA and only initializing it once.
Change-Id: I6d6ab26200c4e781151cc6efd97ce2420e2bf4cc Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6803 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
#
12478:604310e2d7ad |
|
03-Nov-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: extend MiscReg metadata structures
Implement proper handling of RES0/RES1 and RAZ/RAO bitfields.
Change-Id: I344c32c3fb1d142acfb0521ba3590ddd2b1f5360 Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6802 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12477:3d6c49bc7290 |
|
06-Dec-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arch-arm: understandably initialize register mappings
The mappings for sharing a backing store between AArch32 and AArch64 system registers are made clearer using an initializer object.
Change-Id: I29dcfab2797b4d36b3182342997edffde334a291 Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6801 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12406:86bde4a026b5 |
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22-Dec-2017 |
Gabe Black <gabeblack@google.com> |
arch,cpu: "virtualize" the TLB interface.
CPUs have historically instantiated the architecture specific version of the TLBs to avoid a virtual function call, making them a little bit more dependent on what the current ISA is. Some simple performance measurement, the x86 twolf regression on the atomic CPU, shows that there isn't actually any performance benefit, and if anything the simulator goes slightly faster (although still within margin of error) when the TLB functions are virtual.
This change switches everything outside of the architectures themselves to use the generic BaseTLB type, and then inside the ISA for them to cast that to their architecture specific type to call into architecture specific interfaces.
The ARM TLB needed the most adjustment since it was using non-standard translation function signatures. Specifically, they all took an extra "type" parameter which defaulted to normal, and translateTiming returned a Fault. translateTiming actually doesn't need to return a Fault because everywhere that consumed it just stored it into a structure which it then deleted(?), and the fault is stored in the Translation object when the translation is done.
A little more work is needed to fully obviate the arch/tlb.hh header, so the TheISA::TLB type is still visible outside of the ISAs. Specifically, the TlbEntry type is used in the generic PageTable which lives in src/mem.
Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575 Reviewed-on: https://gem5-review.googlesource.com/6921 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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#
12392:e0dbdf30a2a5 |
|
13-Dec-2017 |
Jason Lowe-Power <jason@lowepower.com> |
misc: Updates for gcc7.2 for x86
GCC 7.2 is much stricter than previous GCC versions. The following changes are needed:
* There is now a warning if there is an implicit fallthrough between two case statments. C++17 adds the [[fallthrough]]; declaration. However, to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH. M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and if that doesn't exist, it defaults to nothing (no older compilers generate warnings). * The above resulted in a couple of bugs that were found. This is noted in the review request on gerrit. * throw() for dynamic exception specification is deprecated * There were a couple of new uninitialized variable warnings * Can no longer perform bitwise operations on a bool. * Must now include <functional> for std::function * Compiler bug for void* lambda. Changed to auto as work around. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878
Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5802 Reviewed-by: Gabe Black <gabeblack@google.com>
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#
12109:f29e9c5418aa |
|
05-Apr-2017 |
Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> |
cpu: Added interface for vector reg file
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file.
This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation.
This requires implementing the vector register file for the different models using the VecRegContainer class.
This change set also updates the Result abstraction to contemplate the possibility of having a vector as result.
The changes also affect how the remote_gdb connection works.
There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions.
Nathanael Premillieu's work with an increasing number of fixes and improvements of mine.
Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
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#
11809:61c625151d9a |
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09-Feb-2017 |
Bjoern A. Zeeb <baz21@cam.ac.uk> |
arm: AArch64 report cache size correctly when reading CTR_EL0
Trying to read MISCREG_CTR_EL0 on AArch64 returned 0 as is was not implmemented. With that an operating system relying on the cache line sizes reported in order to manage the caches would (a) panic given the returned value 0 is not valid (high bit is RES1) or (b) worst case would assume a cache line size of 4 doing a tremendous amount of extra instruction work (including fetching). Return the same values as for ARMv7 as the fields seem to be the same, or RES0/1 seem to be reported accordingly for AArch64
In collaboration with: Andrew Turner
Testing Done: Checked on FreeBSD boots with extra printfs; also observed a reduction of a factor of about 10 in instruction fetches for a simple micro-test.
Reviewed at http://reviews.gem5.org/r/3667/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
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#
11793:ef606668d247 |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes
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#
11774:4b62a0bf0168 |
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19-Dec-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: provide correct timer availability in ID_PFR1 register
Change-Id: Id4cd839c12b70616017a5830e3f9bbb59b0f97ba Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11773:9db50b9eacf5 |
|
19-Dec-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: compute ID_AA64PFR{0,1}_EL1 registers
Compute the proper values of the aforementioned registers from the system configuration rather than configuring the values themselves.
Change-Id: If9774b6610a29568b80ae4866107b9a6a5b5be0f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11772:baccae81e57e |
|
19-Dec-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: compute ID_PFR{0,1} registers
Compute the proper values of the aforementioned registers from the system configuration rather than configuring the values themselves.
Change-Id: Ie7685b5d8b5f2dd9d6380b4af74f16d596b2bfd1 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11771:764eae95bbbb |
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19-Dec-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: miscreg refactoring
Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11770:0d7119bed18e |
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19-Dec-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: audit SCTLR
Change-Id: I814f1431a5f754f75721c9ac51171f860a714d24 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11769:ec57caae355e |
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19-Dec-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: remove SCTLR.FI
Removed from ARMARM.
Change-Id: Ie8f28e4fa6e1b46dfd9c8c4b379e5b42fe25421d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11768:5b80960dcf08 |
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19-Dec-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: update AArch{64,32} register mappings
Change-Id: Idaaaeb3f7b1a0bdbf18d8e2d46686c78bb411317 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11608:6319a1125f1c |
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14-Aug-2016 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
cpu, arch: fix the type used for the request flags
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11584:bbd8448f104e |
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02-Aug-2016 |
Dylan Johnson <Dylan.Johnson@ARM.com> |
arm: Add TLBI instruction for stage 2 IPA's
This patch adds support for stage 2 TLBI instructions such as TLBI IPAS2E1_Xt.
Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
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#
11577:a26a328c20eb |
|
02-Aug-2016 |
Dylan Johnson <Dylan.Johnson@ARM.com> |
arm: Fix EL perceived at TLB for address translation instructions
During address translation instructions (such as AT S1E1R_Xt) the exception level can be different than the current exception level. This patch fixes how the TLB determines what EL to use during these instructions.
Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f
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#
11575:0005b28685f0 |
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02-Aug-2016 |
Dylan Johnson <Dylan.Johnson@ARM.com> |
arm: add stage2 translation support
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
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#
11574:868c31fcca24 |
|
02-Aug-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
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#
11573:cc3252906757 |
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02-Aug-2016 |
Dylan Johnson <Dylan.Johnson@ARM.com> |
arm: invalidate TLB miscreg cache on modification of HSCTLR
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
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#
11560:f050b8cf4754 |
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11-Jul-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm: Don't consult the TLB test iface for functional translations
Don't consult the TLB test interface for PA's returned by functional translations by the AT instruction. We implement this by chaning the ISA code to synthesize 0-length functional reads for the TLB lookup. The TLB then bypasses the final PA check in the tester if the size is zero.
Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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#
11435:0f1b46dde3fa |
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07-Apr-2016 |
Mitch Hayenga <mitch.hayenga@arm.com> |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu.
This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
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#
11429:cf5af0cc3be4 |
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06-Apr-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
Revert power patch sets with unexpected interactions
The following patches had unexpected interactions with the current upstream code and have been reverted for now:
e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11428:20264eb69fbf |
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05-Apr-2016 |
Mitch Hayenga <mitch.hayenga@arm.com> |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu.
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#
11165:d90aec9435bd |
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09-Oct-2015 |
Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> |
isa: Add parameter to pick different decoder inside ISA
The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time.
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#
11150:a8a64cca231b |
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30-Sep-2015 |
Mitch Hayenga <mitch.hayenga@arm.com> |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
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#
10870:b3dfb40bb2ab |
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09-Jun-2015 |
Rune Holm <rune.holm@arm.com> |
arm: Delete debug print in initialization of hardware thread
There seems to have been a debug print left in when the original ARMv8 support was merged in. This printout is performed every time you initialize a hardware thread, and it prints raw pointers, so it always causes diffs in the regression. This patch removes the debug print.
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#
10844:8551af601f75 |
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23-May-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Refactor and clean up the generic timer model
This changeset cleans up the generic timer a bit and moves most of the register juggling from the ISA code into a separate class in the same source file as the rest of the generic timer. It also removes the assumption that there is always 8 or fewer CPUs in the system. Instead of having a fixed limit, we now instantiate per-core timers as they are requested. This is all in preparation for other patches that add support for virtual timers and a memory mapped interface.
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#
10822:d259f2bc2b31 |
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05-May-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
arm: Remove unnecessary boot uncachability
With the recent patches addressing how we deal with uncacheable accesses there is no longer need for the work arounds put in place to enforce certain sections of memory to be uncacheable during boot.
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#
10709:890269a13188 |
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02-Mar-2015 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
arm: Don't truncate 16-bit ASIDs to 8 bits
The ISA code sometimes stores 16-bit ASIDs as 8-bit unsigned integers and has a couple of inverted checks that mask out the high 8 bits of an ASID if 16-bit ASIDs have been /enabled/. This changeset fixes both of those issues.
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#
10653:e3fc6bc7f97e |
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22-Jan-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Clean up Request initialisation
This patch tidies up how we create and set the fields of a Request. In essence it tries to use the constructor where possible (as opposed to setPhys and setVirt), thus avoiding spreading the information across a number of locations. In fact, setPhys is made private as part of this patch, and a number of places where we callede setVirt instead uses the appropriate constructor.
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#
10609:ae5582819481 |
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23-Dec-2014 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm: Add support for filtering in the PMU
This patch adds support for filtering events in the PMU. In order to do so, it updates the ISADevice base class to forward an ISA pointer to ISA devices. This enables such devices to access the MiscReg file to determine the current execution level.
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#
10508:aa46a8ae3487 |
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30-Oct-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file. Check SCTLR_EL1 to verify all caches are enabled.
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#
10461:afeb5cdb3907 |
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16-Oct-2014 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
arm: Add a model of an ARM PMUv3
This class implements a subset of the ARM PMU v3 specification as described in the ARMv8 reference manual. It supports most of the features of the PMU, however the following features are known to be missing:
* Event filtering (e.g., from different privilege levels). * Access controls (the PMU currently ignores the execution level). * The chain counter (event no. 0x1E) is unimplemented.
The PMU itself does not implement any events, it merely provides an interface for the configuration scripts to hook up probes that drive events. Configuration scripts should call addEventProbe() to configure custom events or high-level methods to configure architected events. The Python implementation of addEventProbe() automatically delays event type registration until after instantiation.
In order to support CPU switching and some combined counters (e.g., memory references synthesized from loads and stores), the PMU allows multiple probes per event type. When creating a system that switches between CPU models that share the same PMU, PMU events for all of the CPU models can be registered with the PMU.
Kudos to Matt Horsnell for the initial gem5 implementation of the PMU.
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10338:8bee5f4edb92 |
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29-Apr-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version and corresponding upgrader code to move the condition code register values to the new register file.
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10204:82d8f37e5b57 |
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17-Apr-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
arm: allow DC instructions by default so SE mode works
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10188:c09802451018 |
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09-May-2014 |
Geoffrey Blake <geoffrey.blake@arm.com> |
arm: Panics in miscreg read functions can be tripped by O3 model
Unimplemented miscregs for the generic timer were guarded by panics in arm/isa.cc which can be tripped by the O3 model if it speculatively executes a wrong path containing a mrs instruction with a bad miscreg index. These registers were flagged as implemented and accessible. This patch changes the miscreg info bit vector to flag them as unimplemented and inaccessible. In this case, and UndefinedInst fault will be generated if the register access is not trapped by a hypervisor.
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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10035:2a0fbecfeb14 |
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24-Jan-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Make all register index flattening const
This patch makes all the register index flattening methods const for all the ISAs. As part of this, readMiscRegNoEffect for ARM is also made const.
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9814:7ad2b0186a32 |
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18-Jul-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets the cache line size on the system level.
Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used.
A follow-on patch updates the configuration scripts accordingly.
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9431:8bb372a49e1b |
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07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
arm: Remove the register mapping hack used when copying TCs
In order to see all registers independent of the current CPU mode, the ARM architecture model uses the magic MISCREG_CPSR_MODE register to change the register mappings without actually updating the CPU mode. This hack is no longer needed since the thread context now provides a flat interface to the register file. This patch replaces the CPSR_MODE hack with the flat register interface.
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9385:25ebe5e13a07 |
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07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
arm: Make ID registers ISA parameters
This patch makes the values of ID_ISARx, MIDR, and FPSID configurable as ISA parameter values. Additionally, setMiscReg now ignores writes to all of the ID registers.
Note: This moves the MIDR parameter from ArmSystem to ArmISA for consistency.
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9384:877293183bdf |
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07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
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9377:6f294e7a93d1 |
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04-Jan-2013 |
Gabe Black <gblack@eecs.umich.edu> |
Decoder: Remove the thread context get/set from the decoder.
This interface is no longer used, and getting rid of it simplifies the decoders and code that sets up the decoders. The thread context had been used to read architectural state which was used to contextualize the instruction memory as it came in. That was changed so that the state is now sent to the decoders to keep locally if/when it changes. That's significantly more efficient.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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9374:227a38f9d98c |
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04-Jan-2013 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Keep a copy of the fpscr len and stride fields in the decoder. Avoid reading them every instruction, and also eliminate the last use of the thread context in the decoders.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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9130:8423aa8c2216 |
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27-Jul-2012 |
Anthony Gutierrez <atgutier@umich.edu> |
ARM: fix value of MISCREG_CTR returned by readMiscReg()
According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines) [31:29] Format - b100 specifies v7 [28] RAZ - b0 [27:24] CWG log2(max writeback size #words) - 0x4 16 words [23:20] ERG log2(max reservation size #words) - 0x4 16 words [19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words [15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT [13:4] RAZ - b0000000000 [3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
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9050:ed4378739b6e |
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05-Jun-2012 |
Chander Sudanthi <chander.sudanthi@arm.com> |
ARM: Fix MPIDR and MIDR register implementation.
This change allows designating a system as MP capable or not as some bootloaders/kernels care that it's set right. You can have a single processor MP capable system, but you can't have a multi-processor UP only system. This change also fixes the initialization of the MIDR register.
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8887:20ea02da9c53 |
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09-Mar-2012 |
Geoffrey Blake <geoffrey.blake@arm.com> |
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
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8873:f349cc840cab |
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02-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
New kernel code verifies that multi-processor extensions are available before booting secondary CPUs.
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8870:f95c4042f2d0 |
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01-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
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8868:26dbd171754e |
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01-Mar-2012 |
Matt Horsnell <Matt.Horsnell@arm.com> |
ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
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8832:247fee427324 |
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12-Feb-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python.
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8733:64a7bf8fa56c |
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31-Jan-2012 |
Geoffrey Blake <geoffrey.blake@arm.com> |
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification.
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8549:7cff2156c998 |
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13-Sep-2011 |
Daniel Johnson <daniel.johnson@arm.com> |
ARM: Implement numcpus bits in L2CTLR register.
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8527:6bac5b04d588 |
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19-Aug-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via cache maintence instructions until all processors enable their MMUs & TLBs. Writes to these locations are manually flushed from the cache to main memory when the occur so that cores operating without their MMU enabled and only issuing uncached accesses can receive the correct data. Unfortuantely, gem5 doesn't support any kind of software directed maintence of the cache. Until such time as that support exists this patch marks the specific cache blocks that need to be coherent as non-cacheable until all CPUs enable their MMU and thus allows gem5 to boot MP systems with caches enabled (a requirement for booting an O3 cpu and thus an O3 CPU regression).
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8520:f9a495adafd9 |
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19-Aug-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for DIV/SDIV instructions.
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8468:5e9530779f60 |
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15-Jul-2011 |
Wade Walker <wade.walker@arm.com> |
ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both registers now return values that are consistent with current ARM implementations.
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8302:9f23d01421de |
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13-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
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8299:64a938a8b7fc |
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13-May-2011 |
Chander Sudanthi <chander.sudanthi@arm.com> |
ARM: Better RealView/Versatile EB platform support.
Add registers and components to better support the VersatileEB board. Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl respectively.
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8284:2fcad6253525 |
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04-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for MP misc regs and broadcast flushes.
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8232:b28d06a175be |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
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8208:45331a355c38 |
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04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.
This change fixes a small bug in the arm copyRegs() code where some registers wouldn't be copied if the processor was in a mode other than MODE_USER. Additionally, this change simplifies the way the O3 switchCpu code works by utilizing TheISA::copyRegs() to copy the required context information rather than the adhoc copying that goes on in the CPU model. The current code makes assumptions about the visibility of int and float registers that aren't true for all architectures in FS mode.
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8206:c3090dc00ddf |
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04-Apr-2011 |
William Wang <William.Wang@arm.com> |
ARM: Cleanup and small fixes to some NEON ops to match the spec.
Only certain bits of the cpacr can be written, some must be equal. Mult instructions that write the same register should do something sane
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8205:7ecbffb674aa |
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04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects.
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8147:ac8ef72e9700 |
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17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Implement the Instruction Set Attribute Registers (ISAR).
The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values
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8059:3bf9cdcfc4ee |
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23-Feb-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Reset simulation statistics when pref counters are reset.
The ARM performance counters are not currently supported by the model. This patch interprets a 'reset performance counters' command to mean 'reset the simulator statistics' instead.
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7783:9b880b40ac10 |
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07-Dec-2010 |
Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> |
O3: Make all instructions that write a misc. register not perform the write until commit.
ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized.
Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
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7757:d7360f5052b2 |
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15-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation.
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7749:859e8bc1cdc2 |
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15-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
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7731:e1eace3a118a |
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08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Keep the warnings to a minimum.
These warnings still need to be addresses, but pages of them is counterproductive.
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7720:65d338a8dba4 |
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31-Oct-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later.
Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
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7692:8173327c9c65 |
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01-Oct-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Clean up use of TBit and JBit.
Rather tha constantly using ULL(1) << PcXBitShift define those directly. Additionally, add some helper functions to further clean up the code.
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7678:f19b6a3a8cec |
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13-Sep-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
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7645:873b90fa0eca |
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25-Aug-2010 |
Ali Saidi <ali.saidi@arm.com> |
ARM: Set the high bits in the part number so it's considered new by some code.
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7644:62873d5c2bfc |
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25-Aug-2010 |
Ali Saidi <ali.saidi@arm.com> |
ARM: Fix VFP enabled checks for mem instructions
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7640:5286a8a469c5 |
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25-Aug-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
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7614:763e836c0e70 |
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23-Aug-2010 |
Min Kyu Jeong <minkyu.jeong@arm.com> |
ARM: Clean up flattening for SPSR adding
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7604:9ac39aa78c33 |
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23-Aug-2010 |
Gene Wu <Gene.Wu@arm.com> |
ARM: Get SCTLR TE bit from reset SCTLR
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7588:d6c8516b49e9 |
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23-Aug-2010 |
Ali Saidi <Ali.Saidi@arm.com> |
ARM: We don't currently support ThumbEE exceptions, so don't report that we do
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7583:665d71561298 |
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23-Aug-2010 |
Ali Saidi <Ali.Saidi@arm.com> |
ARM: Implement some more misc registers
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7442:2dc67291f730 |
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03-Jun-2010 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Fix issue with m5.fast and ARM
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7436:b578349f9371 |
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02-Jun-2010 |
Dam Sunwoo <dam.sunwoo@arm.com> |
ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PCWUR, V2PCWUW,...)
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7427:1267715c2112 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Move the ISA "clear" function into isa.cc.
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7408:ee6949c5bb5b |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.
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7406:ddc26bd4ea7d |
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02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Some TLB bug fixes.
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7405:7a938baf14be |
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02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Move Miscreg functions out of isa.hh
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6333:9425c8a86e5c |
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09-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Fold the MiscRegFile all the way into the ISA object.
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6313:95f69a436c82 |
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09-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
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