isa.cc revision 7720:65d338a8dba4
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "sim/faults.hh"
43
44namespace ArmISA
45{
46
47void
48ISA::clear()
49{
50    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
51
52    memset(miscRegs, 0, sizeof(miscRegs));
53    CPSR cpsr = 0;
54    cpsr.mode = MODE_USER;
55    miscRegs[MISCREG_CPSR] = cpsr;
56    updateRegMap(cpsr);
57
58    SCTLR sctlr = 0;
59    sctlr.te = (bool)sctlr_rst.te;
60    sctlr.nmfi = (bool)sctlr_rst.nmfi;
61    sctlr.v = (bool)sctlr_rst.v;
62    sctlr.u    = 1;
63    sctlr.xp = 1;
64    sctlr.rao2 = 1;
65    sctlr.rao3 = 1;
66    sctlr.rao4 = 1;
67    miscRegs[MISCREG_SCTLR] = sctlr;
68    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
69
70    /* Start with an event in the mailbox */
71    miscRegs[MISCREG_SEV_MAILBOX] = 1;
72
73    /*
74     * Implemented = '5' from "M5",
75     * Variant = 0,
76     */
77    miscRegs[MISCREG_MIDR] =
78        (0x35 << 24) | // Implementor is '5' from "M5"
79        (0 << 20)    | // Variant
80        (0xf << 16)  | // Architecture from CPUID scheme
81        (0xf00 << 4) | // Primary part number
82        (0 << 0)     | // Revision
83        0;
84
85    // Separate Instruction and Data TLBs.
86    miscRegs[MISCREG_TLBTR] = 1;
87
88    MVFR0 mvfr0 = 0;
89    mvfr0.advSimdRegisters = 2;
90    mvfr0.singlePrecision = 2;
91    mvfr0.doublePrecision = 2;
92    mvfr0.vfpExceptionTrapping = 0;
93    mvfr0.divide = 1;
94    mvfr0.squareRoot = 1;
95    mvfr0.shortVectors = 1;
96    mvfr0.roundingModes = 1;
97    miscRegs[MISCREG_MVFR0] = mvfr0;
98
99    MVFR1 mvfr1 = 0;
100    mvfr1.flushToZero = 1;
101    mvfr1.defaultNaN = 1;
102    mvfr1.advSimdLoadStore = 1;
103    mvfr1.advSimdInteger = 1;
104    mvfr1.advSimdSinglePrecision = 1;
105    mvfr1.advSimdHalfPrecision = 1;
106    mvfr1.vfpHalfPrecision = 1;
107    miscRegs[MISCREG_MVFR1] = mvfr1;
108
109    miscRegs[MISCREG_MPIDR] = 0;
110
111    // Reset values of PRRR and NMRR are implementation dependent
112
113    miscRegs[MISCREG_PRRR] =
114        (1 << 19) | // 19
115        (0 << 18) | // 18
116        (0 << 17) | // 17
117        (1 << 16) | // 16
118        (2 << 14) | // 15:14
119        (0 << 12) | // 13:12
120        (2 << 10) | // 11:10
121        (2 << 8)  | // 9:8
122        (2 << 6)  | // 7:6
123        (2 << 4)  | // 5:4
124        (1 << 2)  | // 3:2
125        0;          // 1:0
126    miscRegs[MISCREG_NMRR] =
127        (1 << 30) | // 31:30
128        (0 << 26) | // 27:26
129        (0 << 24) | // 25:24
130        (3 << 22) | // 23:22
131        (2 << 20) | // 21:20
132        (0 << 18) | // 19:18
133        (0 << 16) | // 17:16
134        (1 << 14) | // 15:14
135        (0 << 12) | // 13:12
136        (2 << 10) | // 11:10
137        (0 << 8)  | // 9:8
138        (3 << 6)  | // 7:6
139        (2 << 4)  | // 5:4
140        (0 << 2)  | // 3:2
141        0;          // 1:0
142
143    miscRegs[MISCREG_CPACR] = 0;
144    miscRegs[MISCREG_FPSID] = 0x410430A0;
145    //XXX We need to initialize the rest of the state.
146}
147
148MiscReg
149ISA::readMiscRegNoEffect(int misc_reg)
150{
151    assert(misc_reg < NumMiscRegs);
152
153    int flat_idx;
154    if (misc_reg == MISCREG_SPSR)
155        flat_idx = flattenMiscIndex(misc_reg);
156    else
157        flat_idx = misc_reg;
158    MiscReg val = miscRegs[flat_idx];
159
160    DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
161            misc_reg, flat_idx, val);
162    return val;
163}
164
165
166MiscReg
167ISA::readMiscReg(int misc_reg, ThreadContext *tc)
168{
169    if (misc_reg == MISCREG_CPSR) {
170        CPSR cpsr = miscRegs[misc_reg];
171        PCState pc = tc->pcState();
172        cpsr.j = pc.jazelle() ? 1 : 0;
173        cpsr.t = pc.thumb() ? 1 : 0;
174        return cpsr;
175    }
176    if (misc_reg >= MISCREG_CP15_UNIMP_START &&
177        misc_reg < MISCREG_CP15_END) {
178        panic("Unimplemented CP15 register %s read.\n",
179              miscRegName[misc_reg]);
180    }
181    switch (misc_reg) {
182      case MISCREG_CLIDR:
183        warn("The clidr register always reports 0 caches.\n");
184        break;
185      case MISCREG_CCSIDR:
186        warn("The ccsidr register isn't implemented and "
187                "always reads as 0.\n");
188        break;
189      case MISCREG_ID_PFR0:
190        warn("Returning thumbEE disabled for now since we don't support CP14"
191             "config registers and jumping to ThumbEE vectors\n");
192        return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
193      case MISCREG_ID_MMFR0:
194        return 0x03; //VMSAz7
195      case MISCREG_CTR:
196        return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
197      case MISCREG_ACTLR:
198        warn("Not doing anything for miscreg ACTLR\n");
199        break;
200      case MISCREG_PMCR:
201      case MISCREG_PMCCNTR:
202      case MISCREG_PMSELR:
203        warn("Not doing anyhting for read to miscreg %s\n",
204                miscRegName[misc_reg]);
205        break;
206
207    }
208    return readMiscRegNoEffect(misc_reg);
209}
210
211void
212ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
213{
214    assert(misc_reg < NumMiscRegs);
215
216    int flat_idx;
217    if (misc_reg == MISCREG_SPSR)
218        flat_idx = flattenMiscIndex(misc_reg);
219    else
220        flat_idx = misc_reg;
221    miscRegs[flat_idx] = val;
222
223    DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
224            flat_idx, val);
225}
226
227void
228ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
229{
230    MiscReg newVal = val;
231    if (misc_reg == MISCREG_CPSR) {
232        updateRegMap(val);
233        CPSR cpsr = val;
234        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
235                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
236        PCState pc = tc->pcState();
237        pc.nextThumb(cpsr.t);
238        pc.nextJazelle(cpsr.j);
239        tc->pcState(pc);
240    } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
241        misc_reg < MISCREG_CP15_END) {
242        panic("Unimplemented CP15 register %s wrote with %#x.\n",
243              miscRegName[misc_reg], val);
244    } else {
245        switch (misc_reg) {
246          case MISCREG_ITSTATE:
247            {
248                ITSTATE itstate = newVal;
249                CPSR cpsr = miscRegs[MISCREG_CPSR];
250                cpsr.it1 = itstate.bottom2;
251                cpsr.it2 = itstate.top6;
252                miscRegs[MISCREG_CPSR] = cpsr;
253                DPRINTF(MiscRegs,
254                        "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
255                        (uint8_t)itstate, (uint32_t)cpsr);
256            }
257            break;
258          case MISCREG_CPACR:
259            {
260                CPACR newCpacr = 0;
261                CPACR valCpacr = val;
262                newCpacr.cp10 = valCpacr.cp10;
263                newCpacr.cp11 = valCpacr.cp11;
264                //XXX d32dis isn't implemented. The manual says whether or not
265                //it works is implementation defined.
266                newCpacr.asedis = valCpacr.asedis;
267                newVal = newCpacr;
268            }
269            break;
270          case MISCREG_CSSELR:
271            warn("The csselr register isn't implemented.\n");
272            break;
273          case MISCREG_FPSCR:
274            {
275                const uint32_t ones = (uint32_t)(-1);
276                FPSCR fpscrMask = 0;
277                fpscrMask.ioc = ones;
278                fpscrMask.dzc = ones;
279                fpscrMask.ofc = ones;
280                fpscrMask.ufc = ones;
281                fpscrMask.ixc = ones;
282                fpscrMask.idc = ones;
283                fpscrMask.len = ones;
284                fpscrMask.stride = ones;
285                fpscrMask.rMode = ones;
286                fpscrMask.fz = ones;
287                fpscrMask.dn = ones;
288                fpscrMask.ahp = ones;
289                fpscrMask.qc = ones;
290                fpscrMask.v = ones;
291                fpscrMask.c = ones;
292                fpscrMask.z = ones;
293                fpscrMask.n = ones;
294                newVal = (newVal & (uint32_t)fpscrMask) |
295                         (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
296            }
297            break;
298          case MISCREG_FPEXC:
299            {
300                const uint32_t fpexcMask = 0x60000000;
301                newVal = (newVal & fpexcMask) |
302                         (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
303            }
304            break;
305          case MISCREG_SCTLR:
306            {
307                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
308                SCTLR sctlr = miscRegs[MISCREG_SCTLR];
309                SCTLR new_sctlr = newVal;
310                new_sctlr.nmfi =  (bool)sctlr.nmfi;
311                miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
312                return;
313            }
314          case MISCREG_TLBTR:
315          case MISCREG_MVFR0:
316          case MISCREG_MVFR1:
317          case MISCREG_MPIDR:
318          case MISCREG_FPSID:
319            return;
320          case MISCREG_TLBIALLIS:
321          case MISCREG_TLBIALL:
322            warn("Need to flush all TLBs in MP\n");
323            tc->getITBPtr()->flushAll();
324            tc->getDTBPtr()->flushAll();
325            return;
326          case MISCREG_ITLBIALL:
327            tc->getITBPtr()->flushAll();
328            return;
329          case MISCREG_DTLBIALL:
330            tc->getDTBPtr()->flushAll();
331            return;
332          case MISCREG_TLBIMVAIS:
333          case MISCREG_TLBIMVA:
334            warn("Need to flush all TLBs in MP\n");
335            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
336                    bits(newVal, 7,0));
337            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
338                    bits(newVal, 7,0));
339            return;
340          case MISCREG_TLBIASIDIS:
341          case MISCREG_TLBIASID:
342            warn("Need to flush all TLBs in MP\n");
343            tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
344            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
345            return;
346          case MISCREG_TLBIMVAAIS:
347          case MISCREG_TLBIMVAA:
348            warn("Need to flush all TLBs in MP\n");
349            tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
350            tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
351            return;
352          case MISCREG_ITLBIMVA:
353            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
354                    bits(newVal, 7,0));
355            return;
356          case MISCREG_DTLBIMVA:
357            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
358                    bits(newVal, 7,0));
359            return;
360          case MISCREG_ITLBIASID:
361            tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
362            return;
363          case MISCREG_DTLBIASID:
364            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
365            return;
366          case MISCREG_ACTLR:
367            warn("Not doing anything for write of miscreg ACTLR\n");
368            break;
369          case MISCREG_PMCR:
370          case MISCREG_PMCCNTR:
371          case MISCREG_PMSELR:
372            warn("Not doing anything for write to miscreg %s\n",
373                    miscRegName[misc_reg]);
374            break;
375          case MISCREG_V2PCWPR:
376          case MISCREG_V2PCWPW:
377          case MISCREG_V2PCWUR:
378          case MISCREG_V2PCWUW:
379          case MISCREG_V2POWPR:
380          case MISCREG_V2POWPW:
381          case MISCREG_V2POWUR:
382          case MISCREG_V2POWUW:
383            {
384              RequestPtr req = new Request;
385              unsigned flags;
386              BaseTLB::Mode mode;
387              Fault fault;
388              switch(misc_reg) {
389                  case MISCREG_V2PCWPR:
390                      flags = TLB::MustBeOne;
391                      mode = BaseTLB::Read;
392                      break;
393                  case MISCREG_V2PCWPW:
394                      flags = TLB::MustBeOne;
395                      mode = BaseTLB::Write;
396                      break;
397                  case MISCREG_V2PCWUR:
398                      flags = TLB::MustBeOne | TLB::UserMode;
399                      mode = BaseTLB::Read;
400                      break;
401                  case MISCREG_V2PCWUW:
402                      flags = TLB::MustBeOne | TLB::UserMode;
403                      mode = BaseTLB::Write;
404                      break;
405                  default:
406                      panic("Security Extensions not implemented!");
407              }
408              req->setVirt(0, val, 1, flags, tc->pcState().pc());
409              fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
410              if (fault == NoFault) {
411                  miscRegs[MISCREG_PAR] =
412                      (req->getPaddr() & 0xfffff000) |
413                      (tc->getDTBPtr()->getAttr() );
414                  DPRINTF(MiscRegs,
415                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
416                          val, miscRegs[MISCREG_PAR]);
417              }
418              else {
419                  // Set fault bit and FSR
420                  FSR fsr = miscRegs[MISCREG_DFSR];
421                  miscRegs[MISCREG_PAR] =
422                      (fsr.ext << 6) |
423                      (fsr.fsHigh << 5) |
424                      (fsr.fsLow << 1) |
425                      0x1; // F bit
426              }
427              return;
428            }
429        }
430    }
431    setMiscRegNoEffect(misc_reg, newVal);
432}
433
434}
435