Lines Matching refs:TLB
51 #include "debug/TLB.hh"
62 // RISC-V TLB
65 TLB::TLB(const Params *p)
73 TLB::~TLB()
79 // look up an entry in the TLB
81 TLB::lookup(Addr vpn, uint8_t asn) const
91 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
105 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
111 TLB::getEntry(unsigned Index) const
119 TLB::probeEntry(Addr vpn, uint8_t asn) const
129 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
147 TLB::checkCacheability(const RequestPtr &req)
151 // address or by the TLB entry
160 TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
164 warn("Attempted to write at index (%d) beyond TLB size (%d)",
167 // Update TLB
168 DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
186 // insert a new TLB entry
188 TLB::insert(Addr addr, PTE &pte)
190 fatal("TLB Insert not yet implemented\n");
194 TLB::flushAll()
196 DPRINTF(TLB, "flushAll\n");
203 TLB::serialize(CheckpointOut &cp) const
215 TLB::unserialize(CheckpointIn &cp)
230 TLB::regStats()
287 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
322 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
368 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
377 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
385 TLB::finalizePhysical(const RequestPtr &req,
393 TLB::index(bool advance)
403 RiscvISA::TLB *
406 return new TLB(this);