111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 311723Sar4jc@virginia.edu * Copyright (c) 2007 MIPS Technologies, Inc. 411723Sar4jc@virginia.edu * All rights reserved. 511723Sar4jc@virginia.edu * 611723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 711723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 811723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 911723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1011723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1111723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1211723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1311723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1411723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1511723Sar4jc@virginia.edu * this software without specific prior written permission. 1611723Sar4jc@virginia.edu * 1711723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1811723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1911723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2011723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2111723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2211723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2311723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2411723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2511723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2611723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2711723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2811723Sar4jc@virginia.edu * 2911723Sar4jc@virginia.edu * Authors: Nathan Binkert 3011723Sar4jc@virginia.edu * Steve Reinhardt 3111723Sar4jc@virginia.edu * Jaidev Patwardhan 3211723Sar4jc@virginia.edu * Korey Sewell 3311723Sar4jc@virginia.edu */ 3411723Sar4jc@virginia.edu 3511723Sar4jc@virginia.edu#ifndef __ARCH_RISCV_TLB_HH__ 3611723Sar4jc@virginia.edu#define __ARCH_RISCV_TLB_HH__ 3711723Sar4jc@virginia.edu 3811723Sar4jc@virginia.edu#include <map> 3911723Sar4jc@virginia.edu 4011723Sar4jc@virginia.edu#include "arch/generic/tlb.hh" 4111723Sar4jc@virginia.edu#include "arch/riscv/isa_traits.hh" 4211723Sar4jc@virginia.edu#include "arch/riscv/pagetable.hh" 4311723Sar4jc@virginia.edu#include "arch/riscv/utility.hh" 4411723Sar4jc@virginia.edu#include "arch/riscv/vtophys.hh" 4511723Sar4jc@virginia.edu#include "base/statistics.hh" 4611723Sar4jc@virginia.edu#include "mem/request.hh" 4711723Sar4jc@virginia.edu#include "params/RiscvTLB.hh" 4811723Sar4jc@virginia.edu#include "sim/sim_object.hh" 4911723Sar4jc@virginia.edu 5011723Sar4jc@virginia.educlass ThreadContext; 5111723Sar4jc@virginia.edu 5211723Sar4jc@virginia.edu/* To maintain compatibility with other architectures, we'll 5311723Sar4jc@virginia.edu simply create an ITLB and DTLB that will point to the real TLB */ 5411723Sar4jc@virginia.edunamespace RiscvISA { 5511723Sar4jc@virginia.edu 5611723Sar4jc@virginia.educlass TLB : public BaseTLB 5711723Sar4jc@virginia.edu{ 5811723Sar4jc@virginia.edu protected: 5911723Sar4jc@virginia.edu typedef std::multimap<Addr, int> PageTable; 6011723Sar4jc@virginia.edu PageTable lookupTable; // Quick lookup into page table 6111723Sar4jc@virginia.edu 6211723Sar4jc@virginia.edu RiscvISA::PTE *table; // the Page Table 6311723Sar4jc@virginia.edu int size; // TLB Size 6411723Sar4jc@virginia.edu int nlu; // not last used entry (for replacement) 6511723Sar4jc@virginia.edu 6611723Sar4jc@virginia.edu void nextnlu() { if (++nlu >= size) nlu = 0; } 6711723Sar4jc@virginia.edu RiscvISA::PTE *lookup(Addr vpn, uint8_t asn) const; 6811723Sar4jc@virginia.edu 6911723Sar4jc@virginia.edu mutable Stats::Scalar read_hits; 7011723Sar4jc@virginia.edu mutable Stats::Scalar read_misses; 7111723Sar4jc@virginia.edu mutable Stats::Scalar read_acv; 7211723Sar4jc@virginia.edu mutable Stats::Scalar read_accesses; 7311723Sar4jc@virginia.edu mutable Stats::Scalar write_hits; 7411723Sar4jc@virginia.edu mutable Stats::Scalar write_misses; 7511723Sar4jc@virginia.edu mutable Stats::Scalar write_acv; 7611723Sar4jc@virginia.edu mutable Stats::Scalar write_accesses; 7711723Sar4jc@virginia.edu Stats::Formula hits; 7811723Sar4jc@virginia.edu Stats::Formula misses; 7911723Sar4jc@virginia.edu Stats::Formula accesses; 8011723Sar4jc@virginia.edu 8111723Sar4jc@virginia.edu public: 8211723Sar4jc@virginia.edu typedef RiscvTLBParams Params; 8311723Sar4jc@virginia.edu TLB(const Params *p); 8411723Sar4jc@virginia.edu 8511723Sar4jc@virginia.edu int probeEntry(Addr vpn,uint8_t) const; 8611723Sar4jc@virginia.edu RiscvISA::PTE *getEntry(unsigned) const; 8711723Sar4jc@virginia.edu virtual ~TLB(); 8811723Sar4jc@virginia.edu 8911723Sar4jc@virginia.edu void takeOverFrom(BaseTLB *otlb) override {} 9011723Sar4jc@virginia.edu 9111723Sar4jc@virginia.edu int smallPages; 9211723Sar4jc@virginia.edu int getsize() const { return size; } 9311723Sar4jc@virginia.edu 9411723Sar4jc@virginia.edu RiscvISA::PTE &index(bool advance = true); 9511723Sar4jc@virginia.edu void insert(Addr vaddr, RiscvISA::PTE &pte); 9611723Sar4jc@virginia.edu void insertAt(RiscvISA::PTE &pte, unsigned Index, int _smallPages); 9711723Sar4jc@virginia.edu void flushAll() override; 9811723Sar4jc@virginia.edu void demapPage(Addr vaddr, uint64_t asn) override 9911723Sar4jc@virginia.edu { 10011723Sar4jc@virginia.edu panic("demapPage unimplemented.\n"); 10111723Sar4jc@virginia.edu } 10211723Sar4jc@virginia.edu 10311723Sar4jc@virginia.edu // static helper functions... really 10411723Sar4jc@virginia.edu static bool validVirtualAddress(Addr vaddr); 10511723Sar4jc@virginia.edu 10612749Sgiacomo.travaglini@arm.com static Fault checkCacheability(const RequestPtr &req); 10711723Sar4jc@virginia.edu 10811723Sar4jc@virginia.edu // Checkpointing 10911723Sar4jc@virginia.edu void serialize(CheckpointOut &cp) const override; 11011723Sar4jc@virginia.edu void unserialize(CheckpointIn &cp) override; 11111723Sar4jc@virginia.edu 11211723Sar4jc@virginia.edu void regStats() override; 11311723Sar4jc@virginia.edu 11412406Sgabeblack@google.com Fault translateAtomic( 11512749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, Mode mode) override; 11612406Sgabeblack@google.com void translateTiming( 11712749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, 11812406Sgabeblack@google.com Translation *translation, Mode mode) override; 11912406Sgabeblack@google.com Fault finalizePhysical( 12012749Sgiacomo.travaglini@arm.com const RequestPtr &req, 12112749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const override; 12211723Sar4jc@virginia.edu 12311723Sar4jc@virginia.edu private: 12412749Sgiacomo.travaglini@arm.com Fault translateInst(const RequestPtr &req, ThreadContext *tc); 12512749Sgiacomo.travaglini@arm.com Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write); 12611723Sar4jc@virginia.edu}; 12711723Sar4jc@virginia.edu 12811723Sar4jc@virginia.edu} 12911723Sar4jc@virginia.edu 13011723Sar4jc@virginia.edu 13111723Sar4jc@virginia.edu 13211723Sar4jc@virginia.edu#endif // __RISCV_MEMORY_HH__ 133