111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 311723Sar4jc@virginia.edu * Copyright (c) 2007 MIPS Technologies, Inc. 411723Sar4jc@virginia.edu * All rights reserved. 511723Sar4jc@virginia.edu * 611723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 711723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 811723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 911723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1011723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1111723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1211723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1311723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1411723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1511723Sar4jc@virginia.edu * this software without specific prior written permission. 1611723Sar4jc@virginia.edu * 1711723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1811723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1911723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2011723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2111723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2211723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2311723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2411723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2511723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2611723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2711723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2811723Sar4jc@virginia.edu * 2911723Sar4jc@virginia.edu * Authors: Nathan Binkert 3011723Sar4jc@virginia.edu * Steve Reinhardt 3111723Sar4jc@virginia.edu * Jaidev Patwardhan 3211723Sar4jc@virginia.edu * Zhengxing Li 3311723Sar4jc@virginia.edu * Deyuan Guo 3411723Sar4jc@virginia.edu */ 3511723Sar4jc@virginia.edu 3611723Sar4jc@virginia.edu#include "arch/riscv/tlb.hh" 3711723Sar4jc@virginia.edu 3811723Sar4jc@virginia.edu#include <string> 3911723Sar4jc@virginia.edu#include <vector> 4011723Sar4jc@virginia.edu 4111723Sar4jc@virginia.edu#include "arch/riscv/faults.hh" 4211723Sar4jc@virginia.edu#include "arch/riscv/pagetable.hh" 4311723Sar4jc@virginia.edu#include "arch/riscv/pra_constants.hh" 4412808Srobert.scheffel1@tu-dresden.de#include "arch/riscv/system.hh" 4511723Sar4jc@virginia.edu#include "arch/riscv/utility.hh" 4611723Sar4jc@virginia.edu#include "base/inifile.hh" 4711723Sar4jc@virginia.edu#include "base/str.hh" 4811723Sar4jc@virginia.edu#include "base/trace.hh" 4911723Sar4jc@virginia.edu#include "cpu/thread_context.hh" 5011723Sar4jc@virginia.edu#include "debug/RiscvTLB.hh" 5111723Sar4jc@virginia.edu#include "debug/TLB.hh" 5211723Sar4jc@virginia.edu#include "mem/page_table.hh" 5311723Sar4jc@virginia.edu#include "params/RiscvTLB.hh" 5411723Sar4jc@virginia.edu#include "sim/full_system.hh" 5511723Sar4jc@virginia.edu#include "sim/process.hh" 5611723Sar4jc@virginia.edu 5711723Sar4jc@virginia.eduusing namespace std; 5811723Sar4jc@virginia.eduusing namespace RiscvISA; 5911723Sar4jc@virginia.edu 6011723Sar4jc@virginia.edu/////////////////////////////////////////////////////////////////////// 6111723Sar4jc@virginia.edu// 6211723Sar4jc@virginia.edu// RISC-V TLB 6311723Sar4jc@virginia.edu// 6411723Sar4jc@virginia.edu 6511723Sar4jc@virginia.eduTLB::TLB(const Params *p) 6611723Sar4jc@virginia.edu : BaseTLB(p), size(p->size), nlu(0) 6711723Sar4jc@virginia.edu{ 6811723Sar4jc@virginia.edu table = new PTE[size]; 6911723Sar4jc@virginia.edu memset(table, 0, sizeof(PTE[size])); 7011723Sar4jc@virginia.edu smallPages = 0; 7111723Sar4jc@virginia.edu} 7211723Sar4jc@virginia.edu 7311723Sar4jc@virginia.eduTLB::~TLB() 7411723Sar4jc@virginia.edu{ 7511723Sar4jc@virginia.edu if (table) 7611723Sar4jc@virginia.edu delete [] table; 7711723Sar4jc@virginia.edu} 7811723Sar4jc@virginia.edu 7911723Sar4jc@virginia.edu// look up an entry in the TLB 8011723Sar4jc@virginia.eduRiscvISA::PTE * 8111723Sar4jc@virginia.eduTLB::lookup(Addr vpn, uint8_t asn) const 8211723Sar4jc@virginia.edu{ 8311723Sar4jc@virginia.edu // assume not found... 8411723Sar4jc@virginia.edu PTE *retval = nullptr; 8511723Sar4jc@virginia.edu PageTable::const_iterator i = lookupTable.find(vpn); 8611723Sar4jc@virginia.edu if (i != lookupTable.end()) { 8711723Sar4jc@virginia.edu while (i->first == vpn) { 8811723Sar4jc@virginia.edu int index = i->second; 8911723Sar4jc@virginia.edu PTE *pte = &table[index]; 9011723Sar4jc@virginia.edu 9111723Sar4jc@virginia.edu /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 9211723Sar4jc@virginia.edu Addr Mask = pte->Mask; 9311723Sar4jc@virginia.edu Addr InvMask = ~Mask; 9411723Sar4jc@virginia.edu Addr VPN = pte->VPN; 9511723Sar4jc@virginia.edu if (((vpn & InvMask) == (VPN & InvMask)) && 9611723Sar4jc@virginia.edu (pte->G || (asn == pte->asid))) { 9711723Sar4jc@virginia.edu // We have a VPN + ASID Match 9811723Sar4jc@virginia.edu retval = pte; 9911723Sar4jc@virginia.edu break; 10011723Sar4jc@virginia.edu } 10111723Sar4jc@virginia.edu ++i; 10211723Sar4jc@virginia.edu } 10311723Sar4jc@virginia.edu } 10411723Sar4jc@virginia.edu 10511723Sar4jc@virginia.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 10611723Sar4jc@virginia.edu retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 10711723Sar4jc@virginia.edu return retval; 10811723Sar4jc@virginia.edu} 10911723Sar4jc@virginia.edu 11011723Sar4jc@virginia.eduRiscvISA::PTE* 11111723Sar4jc@virginia.eduTLB::getEntry(unsigned Index) const 11211723Sar4jc@virginia.edu{ 11311723Sar4jc@virginia.edu // Make sure that Index is valid 11411723Sar4jc@virginia.edu assert(Index<size); 11511723Sar4jc@virginia.edu return &table[Index]; 11611723Sar4jc@virginia.edu} 11711723Sar4jc@virginia.edu 11811723Sar4jc@virginia.eduint 11911723Sar4jc@virginia.eduTLB::probeEntry(Addr vpn, uint8_t asn) const 12011723Sar4jc@virginia.edu{ 12111723Sar4jc@virginia.edu // assume not found... 12211723Sar4jc@virginia.edu int Ind = -1; 12311723Sar4jc@virginia.edu PageTable::const_iterator i = lookupTable.find(vpn); 12411723Sar4jc@virginia.edu if (i != lookupTable.end()) { 12511723Sar4jc@virginia.edu while (i->first == vpn) { 12611723Sar4jc@virginia.edu int index = i->second; 12711723Sar4jc@virginia.edu PTE *pte = &table[index]; 12811723Sar4jc@virginia.edu 12911723Sar4jc@virginia.edu /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 13011723Sar4jc@virginia.edu Addr Mask = pte->Mask; 13111723Sar4jc@virginia.edu Addr InvMask = ~Mask; 13211723Sar4jc@virginia.edu Addr VPN = pte->VPN; 13311723Sar4jc@virginia.edu if (((vpn & InvMask) == (VPN & InvMask)) && 13411723Sar4jc@virginia.edu (pte->G || (asn == pte->asid))) { 13511723Sar4jc@virginia.edu // We have a VPN + ASID Match 13611723Sar4jc@virginia.edu Ind = index; 13711723Sar4jc@virginia.edu break; 13811723Sar4jc@virginia.edu } 13911723Sar4jc@virginia.edu ++i; 14011723Sar4jc@virginia.edu } 14111723Sar4jc@virginia.edu } 14211723Sar4jc@virginia.edu DPRINTF(RiscvTLB,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 14311723Sar4jc@virginia.edu return Ind; 14411723Sar4jc@virginia.edu} 14511723Sar4jc@virginia.edu 14611723Sar4jc@virginia.eduinline Fault 14712749Sgiacomo.travaglini@arm.comTLB::checkCacheability(const RequestPtr &req) 14811723Sar4jc@virginia.edu{ 14911723Sar4jc@virginia.edu Addr VAddrUncacheable = 0xA0000000; 15011723Sar4jc@virginia.edu // In MIPS, cacheability is controlled by certain bits of the virtual 15111723Sar4jc@virginia.edu // address or by the TLB entry 15211723Sar4jc@virginia.edu if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 15311723Sar4jc@virginia.edu // mark request as uncacheable 15411723Sar4jc@virginia.edu req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 15511723Sar4jc@virginia.edu } 15611723Sar4jc@virginia.edu return NoFault; 15711723Sar4jc@virginia.edu} 15811723Sar4jc@virginia.edu 15911723Sar4jc@virginia.eduvoid 16011723Sar4jc@virginia.eduTLB::insertAt(PTE &pte, unsigned Index, int _smallPages) 16111723Sar4jc@virginia.edu{ 16211723Sar4jc@virginia.edu smallPages = _smallPages; 16311723Sar4jc@virginia.edu if (Index > size) { 16411723Sar4jc@virginia.edu warn("Attempted to write at index (%d) beyond TLB size (%d)", 16511723Sar4jc@virginia.edu Index, size); 16611723Sar4jc@virginia.edu } else { 16711723Sar4jc@virginia.edu // Update TLB 16811723Sar4jc@virginia.edu DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n", 16911723Sar4jc@virginia.edu Index, pte.Mask << 11, 17011723Sar4jc@virginia.edu ((pte.VPN << 11) | pte.asid), 17111723Sar4jc@virginia.edu ((pte.PFN0 << 6) | (pte.C0 << 3) | 17211723Sar4jc@virginia.edu (pte.D0 << 2) | (pte.V0 <<1) | pte.G), 17311723Sar4jc@virginia.edu ((pte.PFN1 <<6) | (pte.C1 << 3) | 17411723Sar4jc@virginia.edu (pte.D1 << 2) | (pte.V1 <<1) | pte.G)); 17511723Sar4jc@virginia.edu if (table[Index].V0 || table[Index].V1) { 17611723Sar4jc@virginia.edu // Previous entry is valid 17711723Sar4jc@virginia.edu PageTable::iterator i = lookupTable.find(table[Index].VPN); 17811723Sar4jc@virginia.edu lookupTable.erase(i); 17911723Sar4jc@virginia.edu } 18011723Sar4jc@virginia.edu table[Index]=pte; 18111723Sar4jc@virginia.edu // Update fast lookup table 18211723Sar4jc@virginia.edu lookupTable.insert(make_pair(table[Index].VPN, Index)); 18311723Sar4jc@virginia.edu } 18411723Sar4jc@virginia.edu} 18511723Sar4jc@virginia.edu 18611723Sar4jc@virginia.edu// insert a new TLB entry 18711723Sar4jc@virginia.eduvoid 18811723Sar4jc@virginia.eduTLB::insert(Addr addr, PTE &pte) 18911723Sar4jc@virginia.edu{ 19011723Sar4jc@virginia.edu fatal("TLB Insert not yet implemented\n"); 19111723Sar4jc@virginia.edu} 19211723Sar4jc@virginia.edu 19311723Sar4jc@virginia.eduvoid 19411723Sar4jc@virginia.eduTLB::flushAll() 19511723Sar4jc@virginia.edu{ 19611723Sar4jc@virginia.edu DPRINTF(TLB, "flushAll\n"); 19711723Sar4jc@virginia.edu memset(table, 0, sizeof(PTE[size])); 19811723Sar4jc@virginia.edu lookupTable.clear(); 19911723Sar4jc@virginia.edu nlu = 0; 20011723Sar4jc@virginia.edu} 20111723Sar4jc@virginia.edu 20211723Sar4jc@virginia.eduvoid 20311723Sar4jc@virginia.eduTLB::serialize(CheckpointOut &cp) const 20411723Sar4jc@virginia.edu{ 20511723Sar4jc@virginia.edu SERIALIZE_SCALAR(size); 20611723Sar4jc@virginia.edu SERIALIZE_SCALAR(nlu); 20711723Sar4jc@virginia.edu 20811723Sar4jc@virginia.edu for (int i = 0; i < size; i++) { 20911723Sar4jc@virginia.edu ScopedCheckpointSection sec(cp, csprintf("PTE%d", i)); 21011723Sar4jc@virginia.edu table[i].serialize(cp); 21111723Sar4jc@virginia.edu } 21211723Sar4jc@virginia.edu} 21311723Sar4jc@virginia.edu 21411723Sar4jc@virginia.eduvoid 21511723Sar4jc@virginia.eduTLB::unserialize(CheckpointIn &cp) 21611723Sar4jc@virginia.edu{ 21711723Sar4jc@virginia.edu UNSERIALIZE_SCALAR(size); 21811723Sar4jc@virginia.edu UNSERIALIZE_SCALAR(nlu); 21911723Sar4jc@virginia.edu 22011723Sar4jc@virginia.edu for (int i = 0; i < size; i++) { 22111723Sar4jc@virginia.edu ScopedCheckpointSection sec(cp, csprintf("PTE%d", i)); 22211723Sar4jc@virginia.edu table[i].unserialize(cp); 22311723Sar4jc@virginia.edu if (table[i].V0 || table[i].V1) { 22411723Sar4jc@virginia.edu lookupTable.insert(make_pair(table[i].VPN, i)); 22511723Sar4jc@virginia.edu } 22611723Sar4jc@virginia.edu } 22711723Sar4jc@virginia.edu} 22811723Sar4jc@virginia.edu 22911723Sar4jc@virginia.eduvoid 23011723Sar4jc@virginia.eduTLB::regStats() 23111723Sar4jc@virginia.edu{ 23211723Sar4jc@virginia.edu BaseTLB::regStats(); 23311723Sar4jc@virginia.edu 23411723Sar4jc@virginia.edu read_hits 23511723Sar4jc@virginia.edu .name(name() + ".read_hits") 23611723Sar4jc@virginia.edu .desc("DTB read hits") 23711723Sar4jc@virginia.edu ; 23811723Sar4jc@virginia.edu 23911723Sar4jc@virginia.edu read_misses 24011723Sar4jc@virginia.edu .name(name() + ".read_misses") 24111723Sar4jc@virginia.edu .desc("DTB read misses") 24211723Sar4jc@virginia.edu ; 24311723Sar4jc@virginia.edu 24411723Sar4jc@virginia.edu 24511723Sar4jc@virginia.edu read_accesses 24611723Sar4jc@virginia.edu .name(name() + ".read_accesses") 24711723Sar4jc@virginia.edu .desc("DTB read accesses") 24811723Sar4jc@virginia.edu ; 24911723Sar4jc@virginia.edu 25011723Sar4jc@virginia.edu write_hits 25111723Sar4jc@virginia.edu .name(name() + ".write_hits") 25211723Sar4jc@virginia.edu .desc("DTB write hits") 25311723Sar4jc@virginia.edu ; 25411723Sar4jc@virginia.edu 25511723Sar4jc@virginia.edu write_misses 25611723Sar4jc@virginia.edu .name(name() + ".write_misses") 25711723Sar4jc@virginia.edu .desc("DTB write misses") 25811723Sar4jc@virginia.edu ; 25911723Sar4jc@virginia.edu 26011723Sar4jc@virginia.edu 26111723Sar4jc@virginia.edu write_accesses 26211723Sar4jc@virginia.edu .name(name() + ".write_accesses") 26311723Sar4jc@virginia.edu .desc("DTB write accesses") 26411723Sar4jc@virginia.edu ; 26511723Sar4jc@virginia.edu 26611723Sar4jc@virginia.edu hits 26711723Sar4jc@virginia.edu .name(name() + ".hits") 26811723Sar4jc@virginia.edu .desc("DTB hits") 26911723Sar4jc@virginia.edu ; 27011723Sar4jc@virginia.edu 27111723Sar4jc@virginia.edu misses 27211723Sar4jc@virginia.edu .name(name() + ".misses") 27311723Sar4jc@virginia.edu .desc("DTB misses") 27411723Sar4jc@virginia.edu ; 27511723Sar4jc@virginia.edu 27611723Sar4jc@virginia.edu accesses 27711723Sar4jc@virginia.edu .name(name() + ".accesses") 27811723Sar4jc@virginia.edu .desc("DTB accesses") 27911723Sar4jc@virginia.edu ; 28011723Sar4jc@virginia.edu 28111723Sar4jc@virginia.edu hits = read_hits + write_hits; 28211723Sar4jc@virginia.edu misses = read_misses + write_misses; 28311723Sar4jc@virginia.edu accesses = read_accesses + write_accesses; 28411723Sar4jc@virginia.edu} 28511723Sar4jc@virginia.edu 28611723Sar4jc@virginia.eduFault 28712749Sgiacomo.travaglini@arm.comTLB::translateInst(const RequestPtr &req, ThreadContext *tc) 28811723Sar4jc@virginia.edu{ 28912808Srobert.scheffel1@tu-dresden.de if (FullSystem) { 29012808Srobert.scheffel1@tu-dresden.de /** 29112808Srobert.scheffel1@tu-dresden.de * check if we simulate a bare metal system 29212808Srobert.scheffel1@tu-dresden.de * if so, we have no tlb, phys addr == virt addr 29312808Srobert.scheffel1@tu-dresden.de */ 29412808Srobert.scheffel1@tu-dresden.de if (static_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal()) 29512808Srobert.scheffel1@tu-dresden.de req->setFlags(Request::PHYSICAL); 29611723Sar4jc@virginia.edu 29712808Srobert.scheffel1@tu-dresden.de if (req->getFlags() & Request::PHYSICAL) { 29812808Srobert.scheffel1@tu-dresden.de /** 29912808Srobert.scheffel1@tu-dresden.de * we simply set the virtual address to physical address 30012808Srobert.scheffel1@tu-dresden.de */ 30112808Srobert.scheffel1@tu-dresden.de req->setPaddr(req->getVaddr()); 30212808Srobert.scheffel1@tu-dresden.de return checkCacheability(req); 30312808Srobert.scheffel1@tu-dresden.de } else { 30412808Srobert.scheffel1@tu-dresden.de /** 30512808Srobert.scheffel1@tu-dresden.de * as we currently support bare metal only, we throw a panic, 30612808Srobert.scheffel1@tu-dresden.de * if it is not a bare metal system 30712808Srobert.scheffel1@tu-dresden.de */ 30812808Srobert.scheffel1@tu-dresden.de panic("translateInst not implemented in RISC-V.\n"); 30912808Srobert.scheffel1@tu-dresden.de } 31012808Srobert.scheffel1@tu-dresden.de } else { 31112808Srobert.scheffel1@tu-dresden.de Process * p = tc->getProcessPtr(); 31211723Sar4jc@virginia.edu 31312808Srobert.scheffel1@tu-dresden.de Fault fault = p->pTable->translate(req); 31412808Srobert.scheffel1@tu-dresden.de if (fault != NoFault) 31512808Srobert.scheffel1@tu-dresden.de return fault; 31611723Sar4jc@virginia.edu 31712808Srobert.scheffel1@tu-dresden.de return NoFault; 31812808Srobert.scheffel1@tu-dresden.de } 31911723Sar4jc@virginia.edu} 32011723Sar4jc@virginia.edu 32111723Sar4jc@virginia.eduFault 32212749Sgiacomo.travaglini@arm.comTLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) 32311723Sar4jc@virginia.edu{ 32412808Srobert.scheffel1@tu-dresden.de if (FullSystem) { 32512808Srobert.scheffel1@tu-dresden.de /** 32612808Srobert.scheffel1@tu-dresden.de * check if we simulate a bare metal system 32712808Srobert.scheffel1@tu-dresden.de * if so, we have no tlb, phys addr == virt addr 32812808Srobert.scheffel1@tu-dresden.de */ 32912808Srobert.scheffel1@tu-dresden.de if (static_cast<RiscvSystem *>(tc->getSystemPtr())->isBareMetal()) 33012808Srobert.scheffel1@tu-dresden.de req->setFlags(Request::PHYSICAL); 33111723Sar4jc@virginia.edu 33212808Srobert.scheffel1@tu-dresden.de if (req->getFlags() & Request::PHYSICAL) { 33312808Srobert.scheffel1@tu-dresden.de /** 33412808Srobert.scheffel1@tu-dresden.de * we simply set the virtual address to physical address 33512808Srobert.scheffel1@tu-dresden.de */ 33612808Srobert.scheffel1@tu-dresden.de req->setPaddr(req->getVaddr()); 33712808Srobert.scheffel1@tu-dresden.de return checkCacheability(req); 33812808Srobert.scheffel1@tu-dresden.de } else { 33912808Srobert.scheffel1@tu-dresden.de /** 34012808Srobert.scheffel1@tu-dresden.de * as we currently support bare metal only, we throw a panic, 34112808Srobert.scheffel1@tu-dresden.de * if it is not a bare metal system 34212808Srobert.scheffel1@tu-dresden.de */ 34312808Srobert.scheffel1@tu-dresden.de panic("translateData not implemented in RISC-V.\n"); 34412808Srobert.scheffel1@tu-dresden.de } 34512808Srobert.scheffel1@tu-dresden.de } else { 34612808Srobert.scheffel1@tu-dresden.de // In the O3 CPU model, sometimes a memory access will be speculatively 34712808Srobert.scheffel1@tu-dresden.de // executed along a branch that will end up not being taken where the 34812808Srobert.scheffel1@tu-dresden.de // address is invalid. In that case, return a fault rather than trying 34912808Srobert.scheffel1@tu-dresden.de // to translate it (which will cause a panic). Since RISC-V allows 35012808Srobert.scheffel1@tu-dresden.de // unaligned memory accesses, this should only happen if the request's 35112808Srobert.scheffel1@tu-dresden.de // length is long enough to wrap around from the end of the memory to 35212808Srobert.scheffel1@tu-dresden.de // the start. 35312808Srobert.scheffel1@tu-dresden.de assert(req->getSize() > 0); 35412808Srobert.scheffel1@tu-dresden.de if (req->getVaddr() + req->getSize() - 1 < req->getVaddr()) 35512808Srobert.scheffel1@tu-dresden.de return make_shared<GenericPageTableFault>(req->getVaddr()); 35611962Sar4jc@virginia.edu 35712808Srobert.scheffel1@tu-dresden.de Process * p = tc->getProcessPtr(); 35811723Sar4jc@virginia.edu 35912808Srobert.scheffel1@tu-dresden.de Fault fault = p->pTable->translate(req); 36012808Srobert.scheffel1@tu-dresden.de if (fault != NoFault) 36112808Srobert.scheffel1@tu-dresden.de return fault; 36211723Sar4jc@virginia.edu 36312808Srobert.scheffel1@tu-dresden.de return NoFault; 36412808Srobert.scheffel1@tu-dresden.de } 36511723Sar4jc@virginia.edu} 36611723Sar4jc@virginia.edu 36711723Sar4jc@virginia.eduFault 36812749Sgiacomo.travaglini@arm.comTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 36911723Sar4jc@virginia.edu{ 37011723Sar4jc@virginia.edu if (mode == Execute) 37111723Sar4jc@virginia.edu return translateInst(req, tc); 37211723Sar4jc@virginia.edu else 37311723Sar4jc@virginia.edu return translateData(req, tc, mode == Write); 37411723Sar4jc@virginia.edu} 37511723Sar4jc@virginia.edu 37611723Sar4jc@virginia.eduvoid 37712749Sgiacomo.travaglini@arm.comTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, 37811723Sar4jc@virginia.edu Translation *translation, Mode mode) 37911723Sar4jc@virginia.edu{ 38011723Sar4jc@virginia.edu assert(translation); 38111723Sar4jc@virginia.edu translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 38211723Sar4jc@virginia.edu} 38311723Sar4jc@virginia.edu 38411723Sar4jc@virginia.eduFault 38512749Sgiacomo.travaglini@arm.comTLB::finalizePhysical(const RequestPtr &req, 38612749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const 38711723Sar4jc@virginia.edu{ 38811723Sar4jc@virginia.edu return NoFault; 38911723Sar4jc@virginia.edu} 39011723Sar4jc@virginia.edu 39111723Sar4jc@virginia.edu 39211723Sar4jc@virginia.eduRiscvISA::PTE & 39311723Sar4jc@virginia.eduTLB::index(bool advance) 39411723Sar4jc@virginia.edu{ 39511723Sar4jc@virginia.edu PTE *pte = &table[nlu]; 39611723Sar4jc@virginia.edu 39711723Sar4jc@virginia.edu if (advance) 39811723Sar4jc@virginia.edu nextnlu(); 39911723Sar4jc@virginia.edu 40011723Sar4jc@virginia.edu return *pte; 40111723Sar4jc@virginia.edu} 40211723Sar4jc@virginia.edu 40311723Sar4jc@virginia.eduRiscvISA::TLB * 40411723Sar4jc@virginia.eduRiscvTLBParams::create() 40511723Sar4jc@virginia.edu{ 40611723Sar4jc@virginia.edu return new TLB(this); 40711723Sar4jc@virginia.edu} 408