Lines Matching refs:TLB
50 #include "debug/TLB.hh"
60 // MIPS TLB
63 TLB::TLB(const Params *p)
71 TLB::~TLB()
77 // look up an entry in the TLB
79 TLB::lookup(Addr vpn, uint8_t asn) const
89 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
103 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
109 TLB::getEntry(unsigned Index) const
117 TLB::probeEntry(Addr vpn, uint8_t asn) const
127 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
145 TLB::checkCacheability(const RequestPtr &req)
149 // address or by the TLB entry
158 TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
162 warn("Attempted to write at index (%d) beyond TLB size (%d)",
165 // Update TLB
166 DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
184 // insert a new TLB entry
186 TLB::insert(Addr addr, PTE &pte)
188 fatal("TLB Insert not yet implemented\n");
192 TLB::flushAll()
194 DPRINTF(TLB, "flushAll\n");
201 TLB::serialize(CheckpointOut &cp) const
213 TLB::unserialize(CheckpointIn &cp)
228 TLB::regStats()
285 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
300 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
315 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
324 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
332 TLB::finalizePhysical(const RequestPtr &req,
340 TLB::index(bool advance)
350 MipsISA::TLB *
353 return new TLB(this);