1/*
2 * Copyright (c) 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Gabrielli
38 */
39
40#ifndef __ARCH_ARM_SVE_MEM_HH__
41#define __ARCH_ARM_SVE_MEM_HH__
42
43#include "arch/arm/insts/static_inst.hh"
44#include "arch/arm/tlb.hh"
45
46namespace ArmISA
47{
48
49class SveMemVecFillSpill : public ArmStaticInst
50{
51  protected:
52    IntRegIndex dest;
53    IntRegIndex base;
54    uint64_t imm;
55
56    /// True if the base register is SP (used for SP alignment checking).
57    bool baseIsSP;
58
59    unsigned memAccessFlags;
60
61    SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst,
62                       OpClass __opClass, IntRegIndex _dest,
63                       IntRegIndex _base, uint64_t _imm)
64        : ArmStaticInst(mnem, _machInst, __opClass),
65          dest(_dest), base(_base), imm(_imm),
66          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
67    {
68        baseIsSP = isSP(_base);
69    }
70
71    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
72};
73
74class SveMemPredFillSpill : public ArmStaticInst
75{
76  protected:
77    IntRegIndex dest;
78    IntRegIndex base;
79    uint64_t imm;
80
81    /// True if the base register is SP (used for SP alignment checking).
82    bool baseIsSP;
83
84    unsigned memAccessFlags;
85
86    SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst,
87                        OpClass __opClass, IntRegIndex _dest,
88                        IntRegIndex _base, uint64_t _imm)
89        : ArmStaticInst(mnem, _machInst, __opClass),
90          dest(_dest), base(_base), imm(_imm),
91          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
92    {
93        baseIsSP = isSP(_base);
94    }
95
96    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
97};
98
99class SveContigMemSS : public ArmStaticInst
100{
101  protected:
102    IntRegIndex dest;
103    IntRegIndex gp;
104    IntRegIndex base;
105    IntRegIndex offset;
106
107    /// True if the base register is SP (used for SP alignment checking).
108    bool baseIsSP;
109
110    unsigned memAccessFlags;
111
112    SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
113                   IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
114                   IntRegIndex _offset)
115        : ArmStaticInst(mnem, _machInst, __opClass),
116          dest(_dest), gp(_gp), base(_base), offset(_offset),
117          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
118    {
119        baseIsSP = isSP(_base);
120    }
121
122    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
123};
124
125class SveContigMemSI : public ArmStaticInst
126{
127  protected:
128    IntRegIndex dest;
129    IntRegIndex gp;
130    IntRegIndex base;
131    uint64_t imm;
132
133    /// True if the base register is SP (used for SP alignment checking).
134    bool baseIsSP;
135
136    unsigned memAccessFlags;
137
138    SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
139                   IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
140                   uint64_t _imm)
141        : ArmStaticInst(mnem, _machInst, __opClass),
142          dest(_dest), gp(_gp), base(_base), imm(_imm),
143          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
144    {
145        baseIsSP = isSP(_base);
146    }
147
148    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
149};
150
151}  // namespace ArmISA
152
153#endif  // __ARCH_ARM_SVE_MEM_HH__
154