arch/arm/table_walker.cc

52 #include "debug/TLB.hh"
114     fatal_if(!tlb, "Table walker must have a valid TLB\n");
140     mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc),
191                   uint8_t _vmid, bool _isHyp, TLB::Mode _mode,
192                   TLB::Translation *_trans, bool _timing, bool _functional,
193                   bool secure, TLB::ArmTranslationType tranType,
203         // once per TLB. For timing mode, a new instance is generated for every
204         // TLB miss.
241             TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType);
259      the TLB, all these miscreg reads are expensive */
303     currState->isFetch = (currState->mode == TLB::Execute);
304     currState->isWrite = (currState->mode == TLB::Write);
371     // @TODO Should this always be the TLB or should we look in the stage2 TLB?
377     // instruction has been squashed, or a previous walk has filled the TLB with
416         DPRINTF(TLB, "Squashing table walk for address %#x\n",
462     DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n",
470         DPRINTF(TLB, " - Selecting TTBR0\n");
490         DPRINTF(TLB, " - Selecting TTBR1\n");
514     DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr,
522         DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
561     DPRINTF(TLB, "Beginning table walk for address %#x, TTBCR: %#x\n",
573         DPRINTF(TLB, " - Selecting VTTBR (long-desc.)\n");
578         DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n");
604             DPRINTF(TLB, " - Selecting TTBR0 (long-desc.)\n");
628             DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n");
675         DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n",
682         DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n",
690         DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
743     DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n",
765             DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n");
787                 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
797                 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
816             DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
825             DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
844                 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
945         DPRINTF(TLB, "Address size fault before any lookup\n");
984         DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr_tainted);
1465     DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
1478         DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
1520             DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n",
1585     DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n",
1612         DPRINTF(TLB, "L%d descriptor Invalid, causing fault type %d\n",
1633                 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n",
1640                 DPRINTF(TLB, "L%d descriptor causing Access Fault\n",
1670             DPRINTF(TLB, "L%d descriptor points to L%d descriptor at: %#x (%s)\n",
1679                 DPRINTF(TLB, "L%d descriptor causing Address Size Fault\n",
1743     DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
1750         DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
1775          DPRINTF(TLB, "Generating access fault at L2, afe: %d, ap: %d\n",
1990         flags = flags | TLB::MustBeOne;
2076     // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries
2104     DPRINTF(TLB, descriptor.dbgHeader().c_str());
2105     DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n",
2107     DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d "
2111     DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n",
2115     // Insert the entry into the TLB