16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2001-2005 The Regents of The University of Michigan 36691Stjones1@inf.ed.ac.uk * Copyright (c) 2007 MIPS Technologies, Inc. 46691Stjones1@inf.ed.ac.uk * Copyright (c) 2007-2008 The Florida State University 56691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 66691Stjones1@inf.ed.ac.uk * All rights reserved. 76691Stjones1@inf.ed.ac.uk * 86691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 96691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 106691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 116691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 126691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 136691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 146691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 156691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 166691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 176691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 186691Stjones1@inf.ed.ac.uk * 196691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 206691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 216691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 226691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 236691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 246691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 256691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 266691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 276691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 286691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 296691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 306691Stjones1@inf.ed.ac.uk * 316691Stjones1@inf.ed.ac.uk * Authors: Nathan Binkert 326691Stjones1@inf.ed.ac.uk * Steve Reinhardt 336691Stjones1@inf.ed.ac.uk * Jaidev Patwardhan 346691Stjones1@inf.ed.ac.uk * Stephen Hines 356691Stjones1@inf.ed.ac.uk * Timothy M. Jones 366691Stjones1@inf.ed.ac.uk */ 376691Stjones1@inf.ed.ac.uk 3811793Sbrandon.potter@amd.com#include "arch/power/tlb.hh" 3911793Sbrandon.potter@amd.com 406691Stjones1@inf.ed.ac.uk#include <string> 416691Stjones1@inf.ed.ac.uk#include <vector> 426691Stjones1@inf.ed.ac.uk 436691Stjones1@inf.ed.ac.uk#include "arch/power/faults.hh" 446691Stjones1@inf.ed.ac.uk#include "arch/power/pagetable.hh" 456691Stjones1@inf.ed.ac.uk#include "arch/power/utility.hh" 466691Stjones1@inf.ed.ac.uk#include "base/inifile.hh" 476691Stjones1@inf.ed.ac.uk#include "base/str.hh" 486691Stjones1@inf.ed.ac.uk#include "base/trace.hh" 496691Stjones1@inf.ed.ac.uk#include "cpu/thread_context.hh" 508232Snate@binkert.org#include "debug/Power.hh" 518232Snate@binkert.org#include "debug/TLB.hh" 526691Stjones1@inf.ed.ac.uk#include "mem/page_table.hh" 536691Stjones1@inf.ed.ac.uk#include "params/PowerTLB.hh" 548772Sgblack@eecs.umich.edu#include "sim/full_system.hh" 556691Stjones1@inf.ed.ac.uk#include "sim/process.hh" 566691Stjones1@inf.ed.ac.uk 576691Stjones1@inf.ed.ac.ukusing namespace std; 586691Stjones1@inf.ed.ac.ukusing namespace PowerISA; 596691Stjones1@inf.ed.ac.uk 606691Stjones1@inf.ed.ac.uk/////////////////////////////////////////////////////////////////////// 616691Stjones1@inf.ed.ac.uk// 626691Stjones1@inf.ed.ac.uk// POWER TLB 636691Stjones1@inf.ed.ac.uk// 646691Stjones1@inf.ed.ac.uk 656691Stjones1@inf.ed.ac.uk#define MODE2MASK(X) (1 << (X)) 666691Stjones1@inf.ed.ac.uk 676691Stjones1@inf.ed.ac.ukTLB::TLB(const Params *p) 686691Stjones1@inf.ed.ac.uk : BaseTLB(p), size(p->size), nlu(0) 696691Stjones1@inf.ed.ac.uk{ 706691Stjones1@inf.ed.ac.uk table = new PowerISA::PTE[size]; 716691Stjones1@inf.ed.ac.uk memset(table, 0, sizeof(PowerISA::PTE[size])); 726691Stjones1@inf.ed.ac.uk smallPages = 0; 736691Stjones1@inf.ed.ac.uk} 746691Stjones1@inf.ed.ac.uk 756691Stjones1@inf.ed.ac.ukTLB::~TLB() 766691Stjones1@inf.ed.ac.uk{ 776691Stjones1@inf.ed.ac.uk if (table) 786691Stjones1@inf.ed.ac.uk delete [] table; 796691Stjones1@inf.ed.ac.uk} 806691Stjones1@inf.ed.ac.uk 816691Stjones1@inf.ed.ac.uk// look up an entry in the TLB 826691Stjones1@inf.ed.ac.ukPowerISA::PTE * 836691Stjones1@inf.ed.ac.ukTLB::lookup(Addr vpn, uint8_t asn) const 846691Stjones1@inf.ed.ac.uk{ 856691Stjones1@inf.ed.ac.uk // assume not found... 866691Stjones1@inf.ed.ac.uk PowerISA::PTE *retval = NULL; 876691Stjones1@inf.ed.ac.uk PageTable::const_iterator i = lookupTable.find(vpn); 886691Stjones1@inf.ed.ac.uk if (i != lookupTable.end()) { 896691Stjones1@inf.ed.ac.uk while (i->first == vpn) { 906691Stjones1@inf.ed.ac.uk int index = i->second; 916691Stjones1@inf.ed.ac.uk PowerISA::PTE *pte = &table[index]; 926691Stjones1@inf.ed.ac.uk Addr Mask = pte->Mask; 936691Stjones1@inf.ed.ac.uk Addr InvMask = ~Mask; 946691Stjones1@inf.ed.ac.uk Addr VPN = pte->VPN; 956691Stjones1@inf.ed.ac.uk if (((vpn & InvMask) == (VPN & InvMask)) 966691Stjones1@inf.ed.ac.uk && (pte->G || (asn == pte->asid))) { 976691Stjones1@inf.ed.ac.uk 986691Stjones1@inf.ed.ac.uk // We have a VPN + ASID Match 996691Stjones1@inf.ed.ac.uk retval = pte; 1006691Stjones1@inf.ed.ac.uk break; 1016691Stjones1@inf.ed.ac.uk } 1026691Stjones1@inf.ed.ac.uk ++i; 1036691Stjones1@inf.ed.ac.uk } 1046691Stjones1@inf.ed.ac.uk } 1056691Stjones1@inf.ed.ac.uk 1066691Stjones1@inf.ed.ac.uk DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1076691Stjones1@inf.ed.ac.uk retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 1086691Stjones1@inf.ed.ac.uk return retval; 1096691Stjones1@inf.ed.ac.uk} 1106691Stjones1@inf.ed.ac.uk 1116691Stjones1@inf.ed.ac.ukPowerISA::PTE* 1126691Stjones1@inf.ed.ac.ukTLB::getEntry(unsigned Index) const 1136691Stjones1@inf.ed.ac.uk{ 1146691Stjones1@inf.ed.ac.uk // Make sure that Index is valid 1156691Stjones1@inf.ed.ac.uk assert(Index<size); 1166691Stjones1@inf.ed.ac.uk return &table[Index]; 1176691Stjones1@inf.ed.ac.uk} 1186691Stjones1@inf.ed.ac.uk 1196691Stjones1@inf.ed.ac.ukint 1206691Stjones1@inf.ed.ac.ukTLB::probeEntry(Addr vpn,uint8_t asn) const 1216691Stjones1@inf.ed.ac.uk{ 1226691Stjones1@inf.ed.ac.uk // assume not found... 1236691Stjones1@inf.ed.ac.uk int Ind = -1; 1246691Stjones1@inf.ed.ac.uk PageTable::const_iterator i = lookupTable.find(vpn); 1256691Stjones1@inf.ed.ac.uk if (i != lookupTable.end()) { 1266691Stjones1@inf.ed.ac.uk while (i->first == vpn) { 1276691Stjones1@inf.ed.ac.uk int index = i->second; 1286691Stjones1@inf.ed.ac.uk PowerISA::PTE *pte = &table[index]; 1296691Stjones1@inf.ed.ac.uk Addr Mask = pte->Mask; 1306691Stjones1@inf.ed.ac.uk Addr InvMask = ~Mask; 1316691Stjones1@inf.ed.ac.uk Addr VPN = pte->VPN; 1326691Stjones1@inf.ed.ac.uk if (((vpn & InvMask) == (VPN & InvMask)) 1336691Stjones1@inf.ed.ac.uk && (pte->G || (asn == pte->asid))) { 1346691Stjones1@inf.ed.ac.uk 1356691Stjones1@inf.ed.ac.uk // We have a VPN + ASID Match 1366691Stjones1@inf.ed.ac.uk Ind = index; 1376691Stjones1@inf.ed.ac.uk break; 1386691Stjones1@inf.ed.ac.uk } 1396691Stjones1@inf.ed.ac.uk ++i; 1406691Stjones1@inf.ed.ac.uk } 1416691Stjones1@inf.ed.ac.uk } 1426691Stjones1@inf.ed.ac.uk 1436691Stjones1@inf.ed.ac.uk DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind); 1446691Stjones1@inf.ed.ac.uk return Ind; 1456691Stjones1@inf.ed.ac.uk} 1466691Stjones1@inf.ed.ac.uk 1476691Stjones1@inf.ed.ac.ukinline Fault 14812749Sgiacomo.travaglini@arm.comTLB::checkCacheability(const RequestPtr &req) 1496691Stjones1@inf.ed.ac.uk{ 1506691Stjones1@inf.ed.ac.uk Addr VAddrUncacheable = 0xA0000000; 1516691Stjones1@inf.ed.ac.uk if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 1526691Stjones1@inf.ed.ac.uk 1536691Stjones1@inf.ed.ac.uk // mark request as uncacheable 15410824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 1556691Stjones1@inf.ed.ac.uk } 1566691Stjones1@inf.ed.ac.uk return NoFault; 1576691Stjones1@inf.ed.ac.uk} 1586691Stjones1@inf.ed.ac.uk 1596691Stjones1@inf.ed.ac.ukvoid 1606691Stjones1@inf.ed.ac.ukTLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages) 1616691Stjones1@inf.ed.ac.uk{ 1626691Stjones1@inf.ed.ac.uk smallPages=_smallPages; 1636691Stjones1@inf.ed.ac.uk if (Index > size){ 1646691Stjones1@inf.ed.ac.uk warn("Attempted to write at index (%d) beyond TLB size (%d)", 1656691Stjones1@inf.ed.ac.uk Index, size); 1666691Stjones1@inf.ed.ac.uk } else { 1676691Stjones1@inf.ed.ac.uk 1686691Stjones1@inf.ed.ac.uk // Update TLB 16910231Ssteve.reinhardt@amd.com if (table[Index].V0 || table[Index].V1) { 1706691Stjones1@inf.ed.ac.uk 1716691Stjones1@inf.ed.ac.uk // Previous entry is valid 1726691Stjones1@inf.ed.ac.uk PageTable::iterator i = lookupTable.find(table[Index].VPN); 1736691Stjones1@inf.ed.ac.uk lookupTable.erase(i); 1746691Stjones1@inf.ed.ac.uk } 1756691Stjones1@inf.ed.ac.uk table[Index]=pte; 1766691Stjones1@inf.ed.ac.uk 1776691Stjones1@inf.ed.ac.uk // Update fast lookup table 1786691Stjones1@inf.ed.ac.uk lookupTable.insert(make_pair(table[Index].VPN, Index)); 1796691Stjones1@inf.ed.ac.uk } 1806691Stjones1@inf.ed.ac.uk} 1816691Stjones1@inf.ed.ac.uk 1826691Stjones1@inf.ed.ac.uk// insert a new TLB entry 1836691Stjones1@inf.ed.ac.ukvoid 1846691Stjones1@inf.ed.ac.ukTLB::insert(Addr addr, PowerISA::PTE &pte) 1856691Stjones1@inf.ed.ac.uk{ 1866691Stjones1@inf.ed.ac.uk fatal("TLB Insert not yet implemented\n"); 1876691Stjones1@inf.ed.ac.uk} 1886691Stjones1@inf.ed.ac.uk 1896691Stjones1@inf.ed.ac.ukvoid 1906691Stjones1@inf.ed.ac.ukTLB::flushAll() 1916691Stjones1@inf.ed.ac.uk{ 1926691Stjones1@inf.ed.ac.uk DPRINTF(TLB, "flushAll\n"); 1936691Stjones1@inf.ed.ac.uk memset(table, 0, sizeof(PowerISA::PTE[size])); 1946691Stjones1@inf.ed.ac.uk lookupTable.clear(); 1956691Stjones1@inf.ed.ac.uk nlu = 0; 1966691Stjones1@inf.ed.ac.uk} 1976691Stjones1@inf.ed.ac.uk 1986691Stjones1@inf.ed.ac.ukvoid 19910905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 2006691Stjones1@inf.ed.ac.uk{ 2016691Stjones1@inf.ed.ac.uk SERIALIZE_SCALAR(size); 2026691Stjones1@inf.ed.ac.uk SERIALIZE_SCALAR(nlu); 2036691Stjones1@inf.ed.ac.uk 2046691Stjones1@inf.ed.ac.uk for (int i = 0; i < size; i++) { 20510905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", i)); 20610905Sandreas.sandberg@arm.com table[i].serialize(cp); 2076691Stjones1@inf.ed.ac.uk } 2086691Stjones1@inf.ed.ac.uk} 2096691Stjones1@inf.ed.ac.uk 2106691Stjones1@inf.ed.ac.ukvoid 21110905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 2126691Stjones1@inf.ed.ac.uk{ 2136691Stjones1@inf.ed.ac.uk UNSERIALIZE_SCALAR(size); 2146691Stjones1@inf.ed.ac.uk UNSERIALIZE_SCALAR(nlu); 2156691Stjones1@inf.ed.ac.uk 2166691Stjones1@inf.ed.ac.uk for (int i = 0; i < size; i++) { 21710905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("PTE%d", i)); 2186691Stjones1@inf.ed.ac.uk if (table[i].V0 || table[i].V1) { 2196691Stjones1@inf.ed.ac.uk lookupTable.insert(make_pair(table[i].VPN, i)); 2206691Stjones1@inf.ed.ac.uk } 2216691Stjones1@inf.ed.ac.uk } 2226691Stjones1@inf.ed.ac.uk} 2236691Stjones1@inf.ed.ac.uk 2246691Stjones1@inf.ed.ac.ukvoid 2256691Stjones1@inf.ed.ac.ukTLB::regStats() 2266691Stjones1@inf.ed.ac.uk{ 22711523Sdavid.guillen@arm.com BaseTLB::regStats(); 22811523Sdavid.guillen@arm.com 2296691Stjones1@inf.ed.ac.uk read_hits 2306691Stjones1@inf.ed.ac.uk .name(name() + ".read_hits") 2316691Stjones1@inf.ed.ac.uk .desc("DTB read hits") 2326691Stjones1@inf.ed.ac.uk ; 2336691Stjones1@inf.ed.ac.uk 2346691Stjones1@inf.ed.ac.uk read_misses 2356691Stjones1@inf.ed.ac.uk .name(name() + ".read_misses") 2366691Stjones1@inf.ed.ac.uk .desc("DTB read misses") 2376691Stjones1@inf.ed.ac.uk ; 2386691Stjones1@inf.ed.ac.uk 2396691Stjones1@inf.ed.ac.uk 2406691Stjones1@inf.ed.ac.uk read_accesses 2416691Stjones1@inf.ed.ac.uk .name(name() + ".read_accesses") 2426691Stjones1@inf.ed.ac.uk .desc("DTB read accesses") 2436691Stjones1@inf.ed.ac.uk ; 2446691Stjones1@inf.ed.ac.uk 2456691Stjones1@inf.ed.ac.uk write_hits 2466691Stjones1@inf.ed.ac.uk .name(name() + ".write_hits") 2476691Stjones1@inf.ed.ac.uk .desc("DTB write hits") 2486691Stjones1@inf.ed.ac.uk ; 2496691Stjones1@inf.ed.ac.uk 2506691Stjones1@inf.ed.ac.uk write_misses 2516691Stjones1@inf.ed.ac.uk .name(name() + ".write_misses") 2526691Stjones1@inf.ed.ac.uk .desc("DTB write misses") 2536691Stjones1@inf.ed.ac.uk ; 2546691Stjones1@inf.ed.ac.uk 2556691Stjones1@inf.ed.ac.uk 2566691Stjones1@inf.ed.ac.uk write_accesses 2576691Stjones1@inf.ed.ac.uk .name(name() + ".write_accesses") 2586691Stjones1@inf.ed.ac.uk .desc("DTB write accesses") 2596691Stjones1@inf.ed.ac.uk ; 2606691Stjones1@inf.ed.ac.uk 2616691Stjones1@inf.ed.ac.uk hits 2626691Stjones1@inf.ed.ac.uk .name(name() + ".hits") 2636691Stjones1@inf.ed.ac.uk .desc("DTB hits") 2646691Stjones1@inf.ed.ac.uk ; 2656691Stjones1@inf.ed.ac.uk 2666691Stjones1@inf.ed.ac.uk misses 2676691Stjones1@inf.ed.ac.uk .name(name() + ".misses") 2686691Stjones1@inf.ed.ac.uk .desc("DTB misses") 2696691Stjones1@inf.ed.ac.uk ; 2706691Stjones1@inf.ed.ac.uk 2716691Stjones1@inf.ed.ac.uk accesses 2726691Stjones1@inf.ed.ac.uk .name(name() + ".accesses") 2736691Stjones1@inf.ed.ac.uk .desc("DTB accesses") 2746691Stjones1@inf.ed.ac.uk ; 2756691Stjones1@inf.ed.ac.uk 2766691Stjones1@inf.ed.ac.uk hits = read_hits + write_hits; 2776691Stjones1@inf.ed.ac.uk misses = read_misses + write_misses; 2786691Stjones1@inf.ed.ac.uk accesses = read_accesses + write_accesses; 2796691Stjones1@inf.ed.ac.uk} 2806691Stjones1@inf.ed.ac.uk 2816691Stjones1@inf.ed.ac.ukFault 28212749Sgiacomo.travaglini@arm.comTLB::translateInst(const RequestPtr &req, ThreadContext *tc) 2836691Stjones1@inf.ed.ac.uk{ 2846972Stjones1@inf.ed.ac.uk // Instruction accesses must be word-aligned 2856972Stjones1@inf.ed.ac.uk if (req->getVaddr() & 0x3) { 2866972Stjones1@inf.ed.ac.uk DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), 2876972Stjones1@inf.ed.ac.uk req->getSize()); 28810474Sandreas.hansson@arm.com return std::make_shared<AlignmentFault>(); 2896972Stjones1@inf.ed.ac.uk } 2906972Stjones1@inf.ed.ac.uk 2916972Stjones1@inf.ed.ac.uk Process * p = tc->getProcessPtr(); 2926972Stjones1@inf.ed.ac.uk 2936972Stjones1@inf.ed.ac.uk Fault fault = p->pTable->translate(req); 2946972Stjones1@inf.ed.ac.uk if (fault != NoFault) 2956972Stjones1@inf.ed.ac.uk return fault; 2966972Stjones1@inf.ed.ac.uk 2976972Stjones1@inf.ed.ac.uk return NoFault; 2986972Stjones1@inf.ed.ac.uk} 2996972Stjones1@inf.ed.ac.uk 3006972Stjones1@inf.ed.ac.ukFault 30112749Sgiacomo.travaglini@arm.comTLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) 3026972Stjones1@inf.ed.ac.uk{ 3036691Stjones1@inf.ed.ac.uk Process * p = tc->getProcessPtr(); 3046691Stjones1@inf.ed.ac.uk 3056691Stjones1@inf.ed.ac.uk Fault fault = p->pTable->translate(req); 3066691Stjones1@inf.ed.ac.uk if (fault != NoFault) 3076691Stjones1@inf.ed.ac.uk return fault; 3086691Stjones1@inf.ed.ac.uk 3096691Stjones1@inf.ed.ac.uk return NoFault; 3106972Stjones1@inf.ed.ac.uk} 3116972Stjones1@inf.ed.ac.uk 3126972Stjones1@inf.ed.ac.ukFault 31312749Sgiacomo.travaglini@arm.comTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 3146972Stjones1@inf.ed.ac.uk{ 3158806Sgblack@eecs.umich.edu if (FullSystem) 3168772Sgblack@eecs.umich.edu fatal("translate atomic not yet implemented in full system mode.\n"); 3178806Sgblack@eecs.umich.edu 3188806Sgblack@eecs.umich.edu if (mode == Execute) 3198806Sgblack@eecs.umich.edu return translateInst(req, tc); 3208806Sgblack@eecs.umich.edu else 3218806Sgblack@eecs.umich.edu return translateData(req, tc, mode == Write); 3226691Stjones1@inf.ed.ac.uk} 3236691Stjones1@inf.ed.ac.uk 3246691Stjones1@inf.ed.ac.ukvoid 32512749Sgiacomo.travaglini@arm.comTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, 3266691Stjones1@inf.ed.ac.uk Translation *translation, Mode mode) 3276691Stjones1@inf.ed.ac.uk{ 3286691Stjones1@inf.ed.ac.uk assert(translation); 3296691Stjones1@inf.ed.ac.uk translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 3306691Stjones1@inf.ed.ac.uk} 3316691Stjones1@inf.ed.ac.uk 3328888Sgeoffrey.blake@arm.comFault 33312749Sgiacomo.travaglini@arm.comTLB::finalizePhysical(const RequestPtr &req, 33412749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const 3359738Sandreas@sandberg.pp.se{ 3369738Sandreas@sandberg.pp.se return NoFault; 3379738Sandreas@sandberg.pp.se} 3389738Sandreas@sandberg.pp.se 3396691Stjones1@inf.ed.ac.ukPowerISA::PTE & 3406691Stjones1@inf.ed.ac.ukTLB::index(bool advance) 3416691Stjones1@inf.ed.ac.uk{ 3426691Stjones1@inf.ed.ac.uk PowerISA::PTE *pte = &table[nlu]; 3436691Stjones1@inf.ed.ac.uk 3446691Stjones1@inf.ed.ac.uk if (advance) 3456691Stjones1@inf.ed.ac.uk nextnlu(); 3466691Stjones1@inf.ed.ac.uk 3476691Stjones1@inf.ed.ac.uk return *pte; 3486691Stjones1@inf.ed.ac.uk} 3496691Stjones1@inf.ed.ac.uk 3506691Stjones1@inf.ed.ac.ukPowerISA::TLB * 3516691Stjones1@inf.ed.ac.ukPowerTLBParams::create() 3526691Stjones1@inf.ed.ac.uk{ 3536691Stjones1@inf.ed.ac.uk return new PowerISA::TLB(this); 3546691Stjones1@inf.ed.ac.uk} 355