12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302SN/A */ 312SN/A 325569Snate@binkert.org#ifndef __ARCH_ALPHA_TLB_HH__ 335569Snate@binkert.org#define __ARCH_ALPHA_TLB_HH__ 342SN/A 352SN/A#include <map> 362SN/A 372432SN/A#include "arch/alpha/ev5.hh" 381147SN/A#include "arch/alpha/isa_traits.hh" 393453Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 402984Sgblack@eecs.umich.edu#include "arch/alpha/utility.hh" 412984Sgblack@eecs.umich.edu#include "arch/alpha/vtophys.hh" 4210687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 431147SN/A#include "base/statistics.hh" 442517SN/A#include "mem/request.hh" 456022Sgblack@eecs.umich.edu#include "params/AlphaTLB.hh" 462SN/A 472680Sktlim@umich.educlass ThreadContext; 482SN/A 495569Snate@binkert.orgnamespace AlphaISA { 505569Snate@binkert.org 518737Skoansin.tan@gmail.comstruct TlbEntry; 525569Snate@binkert.org 535569Snate@binkert.orgclass TLB : public BaseTLB 542SN/A{ 555569Snate@binkert.org protected: 566022Sgblack@eecs.umich.edu mutable Stats::Scalar fetch_hits; 576022Sgblack@eecs.umich.edu mutable Stats::Scalar fetch_misses; 586022Sgblack@eecs.umich.edu mutable Stats::Scalar fetch_acv; 596022Sgblack@eecs.umich.edu mutable Stats::Formula fetch_accesses; 606022Sgblack@eecs.umich.edu mutable Stats::Scalar read_hits; 616022Sgblack@eecs.umich.edu mutable Stats::Scalar read_misses; 626022Sgblack@eecs.umich.edu mutable Stats::Scalar read_acv; 636022Sgblack@eecs.umich.edu mutable Stats::Scalar read_accesses; 646022Sgblack@eecs.umich.edu mutable Stats::Scalar write_hits; 656022Sgblack@eecs.umich.edu mutable Stats::Scalar write_misses; 666022Sgblack@eecs.umich.edu mutable Stats::Scalar write_acv; 676022Sgblack@eecs.umich.edu mutable Stats::Scalar write_accesses; 686022Sgblack@eecs.umich.edu Stats::Formula data_hits; 696022Sgblack@eecs.umich.edu Stats::Formula data_misses; 706022Sgblack@eecs.umich.edu Stats::Formula data_acv; 716022Sgblack@eecs.umich.edu Stats::Formula data_accesses; 726022Sgblack@eecs.umich.edu 736022Sgblack@eecs.umich.edu 745569Snate@binkert.org typedef std::multimap<Addr, int> PageTable; 755569Snate@binkert.org PageTable lookupTable; // Quick lookup into page table 762SN/A 7710905Sandreas.sandberg@arm.com std::vector<TlbEntry> table; // the Page Table 785569Snate@binkert.org int nlu; // not last used entry (for replacement) 795569Snate@binkert.org 8010905Sandreas.sandberg@arm.com void nextnlu() { if (++nlu >= table.size()) nlu = 0; } 815569Snate@binkert.org TlbEntry *lookup(Addr vpn, uint8_t asn); 825569Snate@binkert.org 835569Snate@binkert.org public: 845569Snate@binkert.org typedef AlphaTLBParams Params; 855569Snate@binkert.org TLB(const Params *p); 865569Snate@binkert.org virtual ~TLB(); 875569Snate@binkert.org 8811169Sandreas.hansson@arm.com void takeOverFrom(BaseTLB *otlb) override {} 8910194SGeoffrey.Blake@arm.com 9011169Sandreas.hansson@arm.com void regStats() override; 916022Sgblack@eecs.umich.edu 9210905Sandreas.sandberg@arm.com int getsize() const { return table.size(); } 935569Snate@binkert.org 945569Snate@binkert.org TlbEntry &index(bool advance = true); 955569Snate@binkert.org void insert(Addr vaddr, TlbEntry &entry); 965569Snate@binkert.org 9711169Sandreas.hansson@arm.com void flushAll() override; 985569Snate@binkert.org void flushProcesses(); 995569Snate@binkert.org void flushAddr(Addr addr, uint8_t asn); 1005569Snate@binkert.org 1015569Snate@binkert.org void 10211169Sandreas.hansson@arm.com demapPage(Addr vaddr, uint64_t asn) override 1033453Sgblack@eecs.umich.edu { 1045569Snate@binkert.org assert(asn < (1 << 8)); 1055569Snate@binkert.org flushAddr(vaddr, asn); 1065569Snate@binkert.org } 1072SN/A 1085569Snate@binkert.org // static helper functions... really EV5 VM traits 1095569Snate@binkert.org static bool 1105569Snate@binkert.org validVirtualAddress(Addr vaddr) 1115569Snate@binkert.org { 1125569Snate@binkert.org // unimplemented bits must be all 0 or all 1 1135569Snate@binkert.org Addr unimplBits = vaddr & VAddrUnImplMask; 1145569Snate@binkert.org return unimplBits == 0 || unimplBits == VAddrUnImplMask; 1155569Snate@binkert.org } 1162SN/A 11712749Sgiacomo.travaglini@arm.com static Fault checkCacheability(const RequestPtr &req, bool itb = false); 1182SN/A 1195569Snate@binkert.org // Checkpointing 12011168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 12111168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1222SN/A 1235569Snate@binkert.org // Most recently used page table entries 1245569Snate@binkert.org TlbEntry *EntryCache[3]; 1255569Snate@binkert.org inline void 1265569Snate@binkert.org flushCache() 1275569Snate@binkert.org { 1285569Snate@binkert.org memset(EntryCache, 0, 3 * sizeof(TlbEntry*)); 1295569Snate@binkert.org } 1302SN/A 1315569Snate@binkert.org inline TlbEntry * 1325569Snate@binkert.org updateCache(TlbEntry *entry) { 1335569Snate@binkert.org EntryCache[2] = EntryCache[1]; 1345569Snate@binkert.org EntryCache[1] = EntryCache[0]; 1355569Snate@binkert.org EntryCache[0] = entry; 1365569Snate@binkert.org return entry; 1375569Snate@binkert.org } 1382SN/A 1395569Snate@binkert.org protected: 14012749Sgiacomo.travaglini@arm.com Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write); 14112749Sgiacomo.travaglini@arm.com Fault translateInst(const RequestPtr &req, ThreadContext *tc); 1422SN/A 1435569Snate@binkert.org public: 14412406Sgabeblack@google.com Fault translateAtomic( 14512749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, Mode mode) override; 14612406Sgabeblack@google.com void translateTiming( 14712749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, 14812406Sgabeblack@google.com Translation *translation, Mode mode) override; 14912406Sgabeblack@google.com Fault finalizePhysical( 15012749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, 15112749Sgiacomo.travaglini@arm.com Mode mode) const override; 1525569Snate@binkert.org}; 1535004Sgblack@eecs.umich.edu 1545569Snate@binkert.org} // namespace AlphaISA 1552SN/A 1565569Snate@binkert.org#endif // __ARCH_ALPHA_TLB_HH__ 157