17405SAli.Saidi@ARM.com/* 214128Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2019 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 4412406Sgabeblack@google.com#include "arch/arm/tlb.hh" 4512605Sgiacomo.travaglini@arm.com#include "arch/arm/tlbi_op.hh" 4611793Sbrandon.potter@amd.com#include "cpu/base.hh" 478887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 488232Snate@binkert.org#include "debug/Arm.hh" 498232Snate@binkert.org#include "debug/MiscRegs.hh" 5010844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh" 5113531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh" 5213531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 539384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 547678Sgblack@eecs.umich.edu#include "sim/faults.hh" 558059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 568284SAli.Saidi@ARM.com#include "sim/system.hh" 577405SAli.Saidi@ARM.com 587405SAli.Saidi@ARM.comnamespace ArmISA 597405SAli.Saidi@ARM.com{ 607405SAli.Saidi@ARM.com 619384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 6210461SAndreas.Sandberg@ARM.com : SimObject(p), 6310461SAndreas.Sandberg@ARM.com system(NULL), 6411165SRekai.GonzalezAlberquilla@arm.com _decoderFlavour(p->decoderFlavour), 6513599Sgiacomo.travaglini@arm.com _vecRegRenameMode(Enums::Full), 6612714Sgiacomo.travaglini@arm.com pmu(p->pmu), 6713691Sgiacomo.travaglini@arm.com haveGICv3CPUInterface(false), 6814000Sgiacomo.travaglini@arm.com impdefAsNop(p->impdef_nop), 6914000Sgiacomo.travaglini@arm.com afterStartup(false) 709384SAndreas.Sandberg@arm.com{ 7111770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = 0; 7210037SARM gem5 Developers 7310461SAndreas.Sandberg@ARM.com // Hook up a dummy device if we haven't been configured with a 7410461SAndreas.Sandberg@ARM.com // real PMU. By using a dummy device, we don't need to check that 7510461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 7610461SAndreas.Sandberg@ARM.com if (!pmu) 7710461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 7810461SAndreas.Sandberg@ARM.com 7910609Sandreas.sandberg@arm.com // Give all ISA devices a pointer to this ISA 8010609Sandreas.sandberg@arm.com pmu->setISA(this); 8110609Sandreas.sandberg@arm.com 8210037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 8310037SARM gem5 Developers 8410037SARM gem5 Developers // Cache system-level properties 8510037SARM gem5 Developers if (FullSystem && system) { 8611771SCurtis.Dunham@arm.com highestELIs64 = system->highestELIs64(); 8710037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8810037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8913173Sgiacomo.travaglini@arm.com haveCrypto = system->haveCrypto(); 9010037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 9110037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 9213114Sgiacomo.travaglini@arm.com physAddrRange = system->physAddrRange(); 9313759Sgiacomo.gabrielli@arm.com haveSVE = system->haveSVE(); 9414128Sgiacomo.travaglini@arm.com havePAN = system->havePAN(); 9513759Sgiacomo.gabrielli@arm.com sveVL = system->sveVL(); 9614133Sjordi.vaquero@metempsy.com haveLSE = system->haveLSE(); 9710037SARM gem5 Developers } else { 9811771SCurtis.Dunham@arm.com highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9910037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 10013499Sgiacomo.travaglini@arm.com haveCrypto = true; 10110037SARM gem5 Developers haveLargeAsid64 = false; 10213114Sgiacomo.travaglini@arm.com physAddrRange = 32; // dummy value 10313759Sgiacomo.gabrielli@arm.com haveSVE = true; 10414128Sgiacomo.travaglini@arm.com havePAN = false; 10513759Sgiacomo.gabrielli@arm.com sveVL = p->sve_vl_se; 10614133Sjordi.vaquero@metempsy.com haveLSE = true; 10710037SARM gem5 Developers } 10810037SARM gem5 Developers 10913599Sgiacomo.travaglini@arm.com // Initial rename mode depends on highestEL 11013599Sgiacomo.travaglini@arm.com const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 11113599Sgiacomo.travaglini@arm.com highestELIs64 ? Enums::Full : Enums::Elem; 11213599Sgiacomo.travaglini@arm.com 11312477SCurtis.Dunham@arm.com initializeMiscRegMetadata(); 11410037SARM gem5 Developers preUnflattenMiscReg(); 11510037SARM gem5 Developers 1169384SAndreas.Sandberg@arm.com clear(); 1179384SAndreas.Sandberg@arm.com} 1189384SAndreas.Sandberg@arm.com 11912479SCurtis.Dunham@arm.comstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 12012479SCurtis.Dunham@arm.com 1219384SAndreas.Sandberg@arm.comconst ArmISAParams * 1229384SAndreas.Sandberg@arm.comISA::params() const 1239384SAndreas.Sandberg@arm.com{ 1249384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 1259384SAndreas.Sandberg@arm.com} 1269384SAndreas.Sandberg@arm.com 1277427Sgblack@eecs.umich.eduvoid 1287427Sgblack@eecs.umich.eduISA::clear() 1297427Sgblack@eecs.umich.edu{ 1309385SAndreas.Sandberg@arm.com const Params *p(params()); 1319385SAndreas.Sandberg@arm.com 1327427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1337427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 13410037SARM gem5 Developers 13513114Sgiacomo.travaglini@arm.com initID32(p); 13610037SARM gem5 Developers 13713114Sgiacomo.travaglini@arm.com // We always initialize AArch64 ID registers even 13813114Sgiacomo.travaglini@arm.com // if we are in AArch32. This is done since if we 13913114Sgiacomo.travaglini@arm.com // are in SE mode we don't know if our ArmProcess is 14013114Sgiacomo.travaglini@arm.com // AArch32 or AArch64 14113114Sgiacomo.travaglini@arm.com initID64(p); 14212690Sgiacomo.travaglini@arm.com 14310037SARM gem5 Developers // Start with an event in the mailbox 1447427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 1457427Sgblack@eecs.umich.edu 14610037SARM gem5 Developers // Separate Instruction and Data TLBs 1477427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 1487427Sgblack@eecs.umich.edu 1497427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1507427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1517427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1527427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1537427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1547427Sgblack@eecs.umich.edu mvfr0.divide = 1; 1557427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1567427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1577427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1587427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1597427Sgblack@eecs.umich.edu 1607427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1617427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1627427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1637427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1647427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1657427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1667427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1677427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1687427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1697427Sgblack@eecs.umich.edu 1707436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1717436Sdam.sunwoo@arm.com 17210037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 17310037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 1747436Sdam.sunwoo@arm.com (1 << 19) | // 19 1757436Sdam.sunwoo@arm.com (0 << 18) | // 18 1767436Sdam.sunwoo@arm.com (0 << 17) | // 17 1777436Sdam.sunwoo@arm.com (1 << 16) | // 16 1787436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1797436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1807436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1817436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1827436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1837436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1847436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1857436Sdam.sunwoo@arm.com 0; // 1:0 18613393Sgiacomo.travaglini@arm.com 18710037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 1887436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1897436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1907436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1917436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1927436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1937436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1947436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1957436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1967436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1977436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1987436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1997436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 2007436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 2017436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 2027436Sdam.sunwoo@arm.com 0; // 1:0 2037436Sdam.sunwoo@arm.com 20413393Sgiacomo.travaglini@arm.com if (FullSystem && system->highestELIs64()) { 20513393Sgiacomo.travaglini@arm.com // Initialize AArch64 state 20613393Sgiacomo.travaglini@arm.com clear64(p); 20713393Sgiacomo.travaglini@arm.com return; 20813393Sgiacomo.travaglini@arm.com } 20913393Sgiacomo.travaglini@arm.com 21013393Sgiacomo.travaglini@arm.com // Initialize AArch32 state... 21113393Sgiacomo.travaglini@arm.com clear32(p, sctlr_rst); 21213393Sgiacomo.travaglini@arm.com} 21313393Sgiacomo.travaglini@arm.com 21413393Sgiacomo.travaglini@arm.comvoid 21513393Sgiacomo.travaglini@arm.comISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 21613393Sgiacomo.travaglini@arm.com{ 21713393Sgiacomo.travaglini@arm.com CPSR cpsr = 0; 21813393Sgiacomo.travaglini@arm.com cpsr.mode = MODE_USER; 21913393Sgiacomo.travaglini@arm.com 22013396Sgiacomo.travaglini@arm.com if (FullSystem) { 22113396Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MVBAR] = system->resetAddr(); 22213396Sgiacomo.travaglini@arm.com } 22313396Sgiacomo.travaglini@arm.com 22413393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_CPSR] = cpsr; 22513393Sgiacomo.travaglini@arm.com updateRegMap(cpsr); 22613393Sgiacomo.travaglini@arm.com 22713393Sgiacomo.travaglini@arm.com SCTLR sctlr = 0; 22813393Sgiacomo.travaglini@arm.com sctlr.te = (bool) sctlr_rst.te; 22913393Sgiacomo.travaglini@arm.com sctlr.nmfi = (bool) sctlr_rst.nmfi; 23013393Sgiacomo.travaglini@arm.com sctlr.v = (bool) sctlr_rst.v; 23113393Sgiacomo.travaglini@arm.com sctlr.u = 1; 23213393Sgiacomo.travaglini@arm.com sctlr.xp = 1; 23313393Sgiacomo.travaglini@arm.com sctlr.rao2 = 1; 23413393Sgiacomo.travaglini@arm.com sctlr.rao3 = 1; 23513393Sgiacomo.travaglini@arm.com sctlr.rao4 = 0xf; // SCTLR[6:3] 23613393Sgiacomo.travaglini@arm.com sctlr.uci = 1; 23713393Sgiacomo.travaglini@arm.com sctlr.dze = 1; 23813393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_NS] = sctlr; 23913393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 24013393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_HCPTR] = 0; 24113393Sgiacomo.travaglini@arm.com 2427644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 2438147SAli.Saidi@ARM.com 2449385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 2459385SAndreas.Sandberg@arm.com 24610037SARM gem5 Developers if (haveLPAE) { 24710037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 24810037SARM gem5 Developers ttbcr.eae = 0; 24910037SARM gem5 Developers miscRegs[MISCREG_TTBCR_NS] = ttbcr; 25010037SARM gem5 Developers // Enforce consistency with system-level settings 25110037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 25210037SARM gem5 Developers } 25310037SARM gem5 Developers 25410037SARM gem5 Developers if (haveSecurity) { 25510037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 25610037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 25710037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 25810037SARM gem5 Developers } else { 25910037SARM gem5 Developers // we're always non-secure 26010037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 26110037SARM gem5 Developers } 2628147SAli.Saidi@ARM.com 2637427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 2647427Sgblack@eecs.umich.edu} 2657427Sgblack@eecs.umich.edu 26610037SARM gem5 Developersvoid 26710037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 26810037SARM gem5 Developers{ 26910037SARM gem5 Developers CPSR cpsr = 0; 27013396Sgiacomo.travaglini@arm.com Addr rvbar = system->resetAddr(); 27110037SARM gem5 Developers switch (system->highestEL()) { 27210037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 27310037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 27410037SARM gem5 Developers // value 27510037SARM gem5 Developers case EL3: 27610037SARM gem5 Developers cpsr.mode = MODE_EL3H; 27710037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 27810037SARM gem5 Developers break; 27910037SARM gem5 Developers case EL2: 28010037SARM gem5 Developers cpsr.mode = MODE_EL2H; 28110037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 28210037SARM gem5 Developers break; 28310037SARM gem5 Developers case EL1: 28410037SARM gem5 Developers cpsr.mode = MODE_EL1H; 28510037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 28610037SARM gem5 Developers break; 28710037SARM gem5 Developers default: 28810037SARM gem5 Developers panic("Invalid highest implemented exception level"); 28910037SARM gem5 Developers break; 29010037SARM gem5 Developers } 29110037SARM gem5 Developers 29210037SARM gem5 Developers // Initialize rest of CPSR 29310037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 29410037SARM gem5 Developers cpsr.ss = 0; 29510037SARM gem5 Developers cpsr.il = 0; 29610037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 29710037SARM gem5 Developers updateRegMap(cpsr); 29810037SARM gem5 Developers 29910037SARM gem5 Developers // Initialize other control registers 30010037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 30110037SARM gem5 Developers if (haveSecurity) { 30211770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 30310037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 30411574SCurtis.Dunham@arm.com } else if (haveVirtualization) { 30511770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 30611770SCurtis.Dunham@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 30710037SARM gem5 Developers } else { 30811770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 30911770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 31010037SARM gem5 Developers // Always non-secure 31110037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 31210037SARM gem5 Developers } 31313114Sgiacomo.travaglini@arm.com} 31410037SARM gem5 Developers 31513114Sgiacomo.travaglini@arm.comvoid 31613114Sgiacomo.travaglini@arm.comISA::initID32(const ArmISAParams *p) 31713114Sgiacomo.travaglini@arm.com{ 31813114Sgiacomo.travaglini@arm.com // Initialize configurable default values 31913114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MIDR] = p->midr; 32013114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MIDR_EL1] = p->midr; 32113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_VPIDR] = p->midr; 32213114Sgiacomo.travaglini@arm.com 32313114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 32413114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 32513114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 32613114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 32713114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 32813114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 32913114Sgiacomo.travaglini@arm.com 33013114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 33113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 33213114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 33313114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 33413499Sgiacomo.travaglini@arm.com 33513499Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5] = insertBits( 33613499Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5], 19, 4, 33713499Sgiacomo.travaglini@arm.com haveCrypto ? 0x1112 : 0x0); 33813114Sgiacomo.travaglini@arm.com} 33913114Sgiacomo.travaglini@arm.com 34013114Sgiacomo.travaglini@arm.comvoid 34113114Sgiacomo.travaglini@arm.comISA::initID64(const ArmISAParams *p) 34213114Sgiacomo.travaglini@arm.com{ 34310037SARM gem5 Developers // Initialize configurable id registers 34410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 34510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 34610461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 34710461SAndreas.Sandberg@ARM.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 34810461SAndreas.Sandberg@ARM.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 34910461SAndreas.Sandberg@ARM.com 35010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 35110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 35210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 35310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 35410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 35513116Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 35610037SARM gem5 Developers 35710461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0_EL1] = 35810461SAndreas.Sandberg@ARM.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 35910461SAndreas.Sandberg@ARM.com 36010461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 36110461SAndreas.Sandberg@ARM.com 36213759Sgiacomo.gabrielli@arm.com // SVE 36313759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 36413759Sgiacomo.gabrielli@arm.com if (haveSecurity) { 36513759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; 36613759Sgiacomo.gabrielli@arm.com } else if (haveVirtualization) { 36713759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; 36813759Sgiacomo.gabrielli@arm.com } else { 36913759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; 37013759Sgiacomo.gabrielli@arm.com } 37113759Sgiacomo.gabrielli@arm.com 37210037SARM gem5 Developers // Enforce consistency with system-level settings... 37310037SARM gem5 Developers 37410037SARM gem5 Developers // EL3 37510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 37711574SCurtis.Dunham@arm.com haveSecurity ? 0x2 : 0x0); 37810037SARM gem5 Developers // EL2 37910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 38010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 38111574SCurtis.Dunham@arm.com haveVirtualization ? 0x2 : 0x0); 38213759Sgiacomo.gabrielli@arm.com // SVE 38313759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 38413759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, 38513759Sgiacomo.gabrielli@arm.com haveSVE ? 0x1 : 0x0); 38610037SARM gem5 Developers // Large ASID support 38710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 38810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 38910037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 39010037SARM gem5 Developers // Physical address size 39110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 39210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 39313114Sgiacomo.travaglini@arm.com encodePhysAddrRange64(physAddrRange)); 39413173Sgiacomo.travaglini@arm.com // Crypto 39513173Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 39613173Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 39713173Sgiacomo.travaglini@arm.com haveCrypto ? 0x1112 : 0x0); 39814133Sjordi.vaquero@metempsy.com // LSE 39914133Sjordi.vaquero@metempsy.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 40014133Sjordi.vaquero@metempsy.com miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20, 40114133Sjordi.vaquero@metempsy.com haveLSE ? 0x2 : 0x0); 40214128Sgiacomo.travaglini@arm.com // PAN 40314128Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits( 40414128Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20, 40514128Sgiacomo.travaglini@arm.com havePAN ? 0x1 : 0x0); 40610037SARM gem5 Developers} 40710037SARM gem5 Developers 40812972Sandreas.sandberg@arm.comvoid 40912972Sandreas.sandberg@arm.comISA::startup(ThreadContext *tc) 41012972Sandreas.sandberg@arm.com{ 41112972Sandreas.sandberg@arm.com pmu->setThreadContext(tc); 41212972Sandreas.sandberg@arm.com 41313531Sjairo.balart@metempsy.com if (system) { 41413531Sjairo.balart@metempsy.com Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 41513531Sjairo.balart@metempsy.com if (gicv3) { 41613691Sgiacomo.travaglini@arm.com haveGICv3CPUInterface = true; 41713531Sjairo.balart@metempsy.com gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 41813531Sjairo.balart@metempsy.com gicv3CpuInterface->setISA(this); 41913826Sgiacomo.travaglini@arm.com gicv3CpuInterface->setThreadContext(tc); 42013531Sjairo.balart@metempsy.com } 42113531Sjairo.balart@metempsy.com } 42214000Sgiacomo.travaglini@arm.com 42314000Sgiacomo.travaglini@arm.com afterStartup = true; 42412972Sandreas.sandberg@arm.com} 42512972Sandreas.sandberg@arm.com 42612972Sandreas.sandberg@arm.com 42713581Sgabeblack@google.comRegVal 42810035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 4297405SAli.Saidi@ARM.com{ 4307405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 4317614Sminkyu.jeong@arm.com 43212478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 43312478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 43412478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 43512478SCurtis.Dunham@arm.com // NB!: apply architectural masks according to desired register, 43612478SCurtis.Dunham@arm.com // despite possibly getting value from different (mapped) register. 43712478SCurtis.Dunham@arm.com auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 43812478SCurtis.Dunham@arm.com |(miscRegs[upper] << 32)); 43912478SCurtis.Dunham@arm.com if (val & reg.res0()) { 44012478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 44112478SCurtis.Dunham@arm.com miscRegName[misc_reg], val & reg.res0()); 44212478SCurtis.Dunham@arm.com } 44312478SCurtis.Dunham@arm.com if ((val & reg.res1()) != reg.res1()) { 44412478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 44512478SCurtis.Dunham@arm.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 44612478SCurtis.Dunham@arm.com } 44712478SCurtis.Dunham@arm.com return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 4487405SAli.Saidi@ARM.com} 4497405SAli.Saidi@ARM.com 4507405SAli.Saidi@ARM.com 45113581Sgabeblack@google.comRegVal 4527405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 4537405SAli.Saidi@ARM.com{ 45410037SARM gem5 Developers CPSR cpsr = 0; 45510037SARM gem5 Developers PCState pc = 0; 45610037SARM gem5 Developers SCR scr = 0; 4579050Schander.sudanthi@arm.com 4587405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 45910037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 46010037SARM gem5 Developers pc = tc->pcState(); 4617720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 4627720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 4637405SAli.Saidi@ARM.com return cpsr; 4647405SAli.Saidi@ARM.com } 4657757SAli.Saidi@ARM.com 46610037SARM gem5 Developers#ifndef NDEBUG 46710037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 46810037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 46910037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 47010037SARM gem5 Developers miscRegName[misc_reg]); 47110037SARM gem5 Developers else 47210037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 47310037SARM gem5 Developers miscRegName[misc_reg]); 47410037SARM gem5 Developers } 47510037SARM gem5 Developers#endif 47610037SARM gem5 Developers 47710037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 47810037SARM gem5 Developers case MISCREG_HCR: 47910037SARM gem5 Developers { 48010037SARM gem5 Developers if (!haveVirtualization) 48110037SARM gem5 Developers return 0; 48210037SARM gem5 Developers else 48310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 48410037SARM gem5 Developers } 48510037SARM gem5 Developers case MISCREG_CPACR: 48610037SARM gem5 Developers { 48710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 48810037SARM gem5 Developers CPACR cpacrMask = 0; 48910037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 49010037SARM gem5 Developers // be readable? (straight copy from the write code) 49110037SARM gem5 Developers cpacrMask.cp10 = ones; 49210037SARM gem5 Developers cpacrMask.cp11 = ones; 49310037SARM gem5 Developers cpacrMask.asedis = ones; 49410037SARM gem5 Developers 49510037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 49610037SARM gem5 Developers if (haveSecurity) { 49710037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 49810037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 49912667Schuan.zhu@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 50010037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 50110037SARM gem5 Developers // NB: Skipping the full loop, here 50210037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 50310037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 50410037SARM gem5 Developers } 50510037SARM gem5 Developers } 50613581Sgabeblack@google.com RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 50710037SARM gem5 Developers val &= cpacrMask; 50810037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 50910037SARM gem5 Developers miscRegName[misc_reg], val); 51010037SARM gem5 Developers return val; 51110037SARM gem5 Developers } 5128284SAli.Saidi@ARM.com case MISCREG_MPIDR: 51310037SARM gem5 Developers case MISCREG_MPIDR_EL1: 51413550Sgiacomo.travaglini@arm.com return readMPIDR(system, tc); 51510037SARM gem5 Developers case MISCREG_VMPIDR: 51613550Sgiacomo.travaglini@arm.com case MISCREG_VMPIDR_EL2: 51710037SARM gem5 Developers // top bit defined as RES1 51810037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 51910037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 52010037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 52110037SARM gem5 Developers case MISCREG_MIDR: 52210037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 52310037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 52410037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 52510037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 52610037SARM gem5 Developers } else { 52710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 5289050Schander.sudanthi@arm.com } 5298284SAli.Saidi@ARM.com break; 53010037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 53110037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 53210037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 53310037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 53410037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 53510037SARM gem5 Developers return 0; 53610037SARM gem5 Developers 5377405SAli.Saidi@ARM.com case MISCREG_CLIDR: 5387731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 5398468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 5408468Swade.walker@arm.com "ARM implementations.\n"); 5418468Swade.walker@arm.com return 0x00200000; 5427405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 5437731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 5447405SAli.Saidi@ARM.com "always reads as 0.\n"); 5457405SAli.Saidi@ARM.com break; 54611809Sbaz21@cam.ac.uk case MISCREG_CTR: // AArch32, ARMv7, top bit set 54711809Sbaz21@cam.ac.uk case MISCREG_CTR_EL0: // AArch64 5489130Satgutier@umich.edu { 5499130Satgutier@umich.edu //all caches have the same line size in gem5 5509130Satgutier@umich.edu //4 byte words in ARM 5519130Satgutier@umich.edu unsigned lineSizeWords = 5529814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 5539130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 5549130Satgutier@umich.edu 5559130Satgutier@umich.edu while (lineSizeWords >>= 1) { 5569130Satgutier@umich.edu ++log2LineSizeWords; 5579130Satgutier@umich.edu } 5589130Satgutier@umich.edu 5599130Satgutier@umich.edu CTR ctr = 0; 5609130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 5619130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 5629130Satgutier@umich.edu //b11 - gem5 uses pipt 5639130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 5649130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 5659130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 5669130Satgutier@umich.edu //log2 of max reservation size (words) 5679130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 5689130Satgutier@umich.edu //log2 of max writeback size (words) 5699130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 5709130Satgutier@umich.edu //b100 - gem5 format is ARMv7 5719130Satgutier@umich.edu ctr.format = 0x4; 5729130Satgutier@umich.edu 5739130Satgutier@umich.edu return ctr; 5749130Satgutier@umich.edu } 5757583SAli.Saidi@arm.com case MISCREG_ACTLR: 5767583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 5777583SAli.Saidi@arm.com break; 57810461SAndreas.Sandberg@ARM.com 57910461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 58010461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 58110461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 58210461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 58310461SAndreas.Sandberg@ARM.com return pmu->readMiscReg(misc_reg); 58410461SAndreas.Sandberg@ARM.com 5858302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 5868302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 5877783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 5887783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5897783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 5907783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 59110037SARM gem5 Developers case MISCREG_FPSR: 59210037SARM gem5 Developers { 59310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 59410037SARM gem5 Developers FPSCR fpscrMask = 0; 59510037SARM gem5 Developers fpscrMask.ioc = ones; 59610037SARM gem5 Developers fpscrMask.dzc = ones; 59710037SARM gem5 Developers fpscrMask.ofc = ones; 59810037SARM gem5 Developers fpscrMask.ufc = ones; 59910037SARM gem5 Developers fpscrMask.ixc = ones; 60010037SARM gem5 Developers fpscrMask.idc = ones; 60110037SARM gem5 Developers fpscrMask.qc = ones; 60210037SARM gem5 Developers fpscrMask.v = ones; 60310037SARM gem5 Developers fpscrMask.c = ones; 60410037SARM gem5 Developers fpscrMask.z = ones; 60510037SARM gem5 Developers fpscrMask.n = ones; 60610037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 60710037SARM gem5 Developers } 60810037SARM gem5 Developers case MISCREG_FPCR: 60910037SARM gem5 Developers { 61010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 61110037SARM gem5 Developers FPSCR fpscrMask = 0; 61210037SARM gem5 Developers fpscrMask.len = ones; 61313759Sgiacomo.gabrielli@arm.com fpscrMask.fz16 = ones; 61410037SARM gem5 Developers fpscrMask.stride = ones; 61510037SARM gem5 Developers fpscrMask.rMode = ones; 61610037SARM gem5 Developers fpscrMask.fz = ones; 61710037SARM gem5 Developers fpscrMask.dn = ones; 61810037SARM gem5 Developers fpscrMask.ahp = ones; 61910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 62010037SARM gem5 Developers } 62110037SARM gem5 Developers case MISCREG_NZCV: 62210037SARM gem5 Developers { 62310037SARM gem5 Developers CPSR cpsr = 0; 62410338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 62510338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 62610338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 62710037SARM gem5 Developers return cpsr; 62810037SARM gem5 Developers } 62910037SARM gem5 Developers case MISCREG_DAIF: 63010037SARM gem5 Developers { 63110037SARM gem5 Developers CPSR cpsr = 0; 63210037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 63310037SARM gem5 Developers return cpsr; 63410037SARM gem5 Developers } 63510037SARM gem5 Developers case MISCREG_SP_EL0: 63610037SARM gem5 Developers { 63710037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 63810037SARM gem5 Developers } 63910037SARM gem5 Developers case MISCREG_SP_EL1: 64010037SARM gem5 Developers { 64110037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 64210037SARM gem5 Developers } 64310037SARM gem5 Developers case MISCREG_SP_EL2: 64410037SARM gem5 Developers { 64510037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 64610037SARM gem5 Developers } 64710037SARM gem5 Developers case MISCREG_SPSEL: 64810037SARM gem5 Developers { 64910037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 65010037SARM gem5 Developers } 65110037SARM gem5 Developers case MISCREG_CURRENTEL: 65210037SARM gem5 Developers { 65310037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 65410037SARM gem5 Developers } 65514128Sgiacomo.travaglini@arm.com case MISCREG_PAN: 65614128Sgiacomo.travaglini@arm.com { 65714128Sgiacomo.travaglini@arm.com return miscRegs[MISCREG_CPSR] & 0x400000; 65814128Sgiacomo.travaglini@arm.com } 6598549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 6608868SMatt.Horsnell@arm.com { 6618868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 6628868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 6638868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 6648868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 6658868SMatt.Horsnell@arm.com return l2ctlr; 6668868SMatt.Horsnell@arm.com } 6678868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 6688868SMatt.Horsnell@arm.com /* For now just implement the version number. 66910461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 6708868SMatt.Horsnell@arm.com */ 67110461SAndreas.Sandberg@ARM.com return 0x5 << 16; 67210037SARM gem5 Developers case MISCREG_DBGDSCRint: 6738868SMatt.Horsnell@arm.com return 0; 67410037SARM gem5 Developers case MISCREG_ISR: 67511150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 67610037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 67710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 67810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 67910037SARM gem5 Developers case MISCREG_ISR_EL1: 68011150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 68110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 68210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 68310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 68410037SARM gem5 Developers case MISCREG_DCZID_EL0: 68510037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 68610037SARM gem5 Developers case MISCREG_HCPTR: 68710037SARM gem5 Developers { 68813581Sgabeblack@google.com RegVal val = readMiscRegNoEffect(misc_reg); 68910037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 69010037SARM gem5 Developers val &= ~(1 << 14); 69110037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 69210037SARM gem5 Developers // HCPTR is RAO/WI 69310037SARM gem5 Developers bool secure_lookup = haveSecurity && 69410037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 69510037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 69610037SARM gem5 Developers if (!secure_lookup) { 69713581Sgabeblack@google.com RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 69810037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 69910037SARM gem5 Developers } 70010037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 70110037SARM gem5 Developers val |= 0x33FF; 70210037SARM gem5 Developers return (val); 70310037SARM gem5 Developers } 70410037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 70510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 70610037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 70710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 70810844Sandreas.sandberg@arm.com 70911772SCurtis.Dunham@arm.com case MISCREG_ID_PFR0: 71011772SCurtis.Dunham@arm.com // !ThumbEE | !Jazelle | Thumb | ARM 71111772SCurtis.Dunham@arm.com return 0x00000031; 71211772SCurtis.Dunham@arm.com case MISCREG_ID_PFR1: 71311774SCurtis.Dunham@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 71411774SCurtis.Dunham@arm.com bool haveTimer = (system->getGenericTimer() != NULL); 71511774SCurtis.Dunham@arm.com return 0x00000001 71611774SCurtis.Dunham@arm.com | (haveSecurity ? 0x00000010 : 0x0) 71711774SCurtis.Dunham@arm.com | (haveVirtualization ? 0x00001000 : 0x0) 71811774SCurtis.Dunham@arm.com | (haveTimer ? 0x00010000 : 0x0); 71911774SCurtis.Dunham@arm.com } 72011773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR0_EL1: 72113531Sjairo.balart@metempsy.com return 0x0000000000000002 | // AArch{64,32} supported at EL0 72213531Sjairo.balart@metempsy.com 0x0000000000000020 | // EL1 72313531Sjairo.balart@metempsy.com (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 72413531Sjairo.balart@metempsy.com (haveSecurity ? 0x0000000000002000 : 0) | // EL3 72513759Sgiacomo.gabrielli@arm.com (haveSVE ? 0x0000000100000000 : 0) | // SVE 72613531Sjairo.balart@metempsy.com (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 72711773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR1_EL1: 72811773SCurtis.Dunham@arm.com return 0; // bits [63:0] RES0 (reserved for future use) 72911772SCurtis.Dunham@arm.com 73010037SARM gem5 Developers // Generic Timer registers 73112816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CTL_EL2: 73212816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CVAL_EL2: 73312816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_TVAL_EL2: 73410844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 73510844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 73610844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 73710844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 73810844Sandreas.sandberg@arm.com return getGenericTimer(tc).readMiscReg(misc_reg); 73910844Sandreas.sandberg@arm.com 74014228Sgiacomo.travaglini@arm.com case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: 74113531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 74213531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 74313531Sjairo.balart@metempsy.com return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 74413531Sjairo.balart@metempsy.com 74510188Sgeoffrey.blake@arm.com default: 74610037SARM gem5 Developers break; 74710037SARM gem5 Developers 7487405SAli.Saidi@ARM.com } 7497405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 7507405SAli.Saidi@ARM.com} 7517405SAli.Saidi@ARM.com 7527405SAli.Saidi@ARM.comvoid 75313582Sgabeblack@google.comISA::setMiscRegNoEffect(int misc_reg, RegVal val) 7547405SAli.Saidi@ARM.com{ 7557405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 7567614Sminkyu.jeong@arm.com 75712478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 75812478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 75912478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 76012478SCurtis.Dunham@arm.com 76112478SCurtis.Dunham@arm.com auto v = (val & ~reg.wi()) | reg.rao(); 76211771SCurtis.Dunham@arm.com if (upper > 0) { 76312478SCurtis.Dunham@arm.com miscRegs[lower] = bits(v, 31, 0); 76412478SCurtis.Dunham@arm.com miscRegs[upper] = bits(v, 63, 32); 76510037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 76612478SCurtis.Dunham@arm.com misc_reg, lower, upper, v); 76710037SARM gem5 Developers } else { 76812478SCurtis.Dunham@arm.com miscRegs[lower] = v; 76910037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 77012478SCurtis.Dunham@arm.com misc_reg, lower, v); 77110037SARM gem5 Developers } 7727405SAli.Saidi@ARM.com} 7737405SAli.Saidi@ARM.com 7747405SAli.Saidi@ARM.comvoid 77513582Sgabeblack@google.comISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 7767405SAli.Saidi@ARM.com{ 7777749SAli.Saidi@ARM.com 77813581Sgabeblack@google.com RegVal newVal = val; 77910037SARM gem5 Developers bool secure_lookup; 78010037SARM gem5 Developers SCR scr; 7818284SAli.Saidi@ARM.com 7827405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 7837405SAli.Saidi@ARM.com updateRegMap(val); 7847749SAli.Saidi@ARM.com 7857749SAli.Saidi@ARM.com 7867749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 7877749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 7887405SAli.Saidi@ARM.com CPSR cpsr = val; 78912510Sgiacomo.travaglini@arm.com if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 79012406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 79112406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 7927749SAli.Saidi@ARM.com } 7937749SAli.Saidi@ARM.com 79414282Sgiacomo.travaglini@arm.com if (cpsr.pan != old_cpsr.pan) { 79514282Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 79614282Sgiacomo.travaglini@arm.com } 79714282Sgiacomo.travaglini@arm.com 7987614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 7997614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 8007720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 8017720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 8027720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 80312763Sgiacomo.travaglini@arm.com pc.illegalExec(cpsr.il == 1); 8048887Sgeoffrey.blake@arm.com 80513759Sgiacomo.gabrielli@arm.com tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); 80613759Sgiacomo.gabrielli@arm.com 8078887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 8088887Sgeoffrey.blake@arm.com // is connected 8098887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 8108887Sgeoffrey.blake@arm.com if (checker) { 8118887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 8128887Sgeoffrey.blake@arm.com } else { 8138887Sgeoffrey.blake@arm.com tc->pcState(pc); 8148887Sgeoffrey.blake@arm.com } 8157408Sgblack@eecs.umich.edu } else { 81610037SARM gem5 Developers#ifndef NDEBUG 81710037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 81810037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 81910037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 82010037SARM gem5 Developers miscRegName[misc_reg], val); 82110037SARM gem5 Developers else 82210037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 82310037SARM gem5 Developers miscRegName[misc_reg], val); 82410037SARM gem5 Developers } 82510037SARM gem5 Developers#endif 82610037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 8277408Sgblack@eecs.umich.edu case MISCREG_CPACR: 8287408Sgblack@eecs.umich.edu { 8298206SWilliam.Wang@arm.com 8308206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 8318206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 8328206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 8338206SWilliam.Wang@arm.com // be writable 8348206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 8358206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 8368206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 83710037SARM gem5 Developers 83810037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 83910037SARM gem5 Developers if (haveSecurity) { 84010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 84110037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 84212667Schuan.zhu@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 84310037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 84410037SARM gem5 Developers // NB: Skipping the full loop, here 84510037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 84610037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 84710037SARM gem5 Developers } 84810037SARM gem5 Developers } 84910037SARM gem5 Developers 85013581Sgabeblack@google.com RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 8518206SWilliam.Wang@arm.com newVal &= cpacrMask; 85210037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 85310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 85410037SARM gem5 Developers miscRegName[misc_reg], newVal); 85510037SARM gem5 Developers } 85610037SARM gem5 Developers break; 85713759Sgiacomo.gabrielli@arm.com case MISCREG_CPACR_EL1: 85813759Sgiacomo.gabrielli@arm.com { 85913759Sgiacomo.gabrielli@arm.com const uint32_t ones = (uint32_t)(-1); 86013759Sgiacomo.gabrielli@arm.com CPACR cpacrMask = 0; 86113759Sgiacomo.gabrielli@arm.com cpacrMask.tta = ones; 86213759Sgiacomo.gabrielli@arm.com cpacrMask.fpen = ones; 86313759Sgiacomo.gabrielli@arm.com if (haveSVE) { 86413759Sgiacomo.gabrielli@arm.com cpacrMask.zen = ones; 86513759Sgiacomo.gabrielli@arm.com } 86613759Sgiacomo.gabrielli@arm.com newVal &= cpacrMask; 86713759Sgiacomo.gabrielli@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 86813759Sgiacomo.gabrielli@arm.com miscRegName[misc_reg], newVal); 86913759Sgiacomo.gabrielli@arm.com } 87013759Sgiacomo.gabrielli@arm.com break; 87110037SARM gem5 Developers case MISCREG_CPTR_EL2: 87210037SARM gem5 Developers { 87310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 87410037SARM gem5 Developers CPTR cptrMask = 0; 87510037SARM gem5 Developers cptrMask.tcpac = ones; 87610037SARM gem5 Developers cptrMask.tta = ones; 87710037SARM gem5 Developers cptrMask.tfp = ones; 87813759Sgiacomo.gabrielli@arm.com if (haveSVE) { 87913759Sgiacomo.gabrielli@arm.com cptrMask.tz = ones; 88013759Sgiacomo.gabrielli@arm.com } 88110037SARM gem5 Developers newVal &= cptrMask; 88210037SARM gem5 Developers cptrMask = 0; 88310037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 88413759Sgiacomo.gabrielli@arm.com cptrMask.res1_7_0_el2 = ones; 88513759Sgiacomo.gabrielli@arm.com if (!haveSVE) { 88613759Sgiacomo.gabrielli@arm.com cptrMask.res1_8_el2 = ones; 88713759Sgiacomo.gabrielli@arm.com } 88813759Sgiacomo.gabrielli@arm.com cptrMask.res1_9_el2 = ones; 88910037SARM gem5 Developers newVal |= cptrMask; 89010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 89110037SARM gem5 Developers miscRegName[misc_reg], newVal); 89210037SARM gem5 Developers } 89310037SARM gem5 Developers break; 89410037SARM gem5 Developers case MISCREG_CPTR_EL3: 89510037SARM gem5 Developers { 89610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 89710037SARM gem5 Developers CPTR cptrMask = 0; 89810037SARM gem5 Developers cptrMask.tcpac = ones; 89910037SARM gem5 Developers cptrMask.tta = ones; 90010037SARM gem5 Developers cptrMask.tfp = ones; 90113759Sgiacomo.gabrielli@arm.com if (haveSVE) { 90213759Sgiacomo.gabrielli@arm.com cptrMask.ez = ones; 90313759Sgiacomo.gabrielli@arm.com } 90410037SARM gem5 Developers newVal &= cptrMask; 9058206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 9068206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 9077408Sgblack@eecs.umich.edu } 9087408Sgblack@eecs.umich.edu break; 9097408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 9107731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 9118206SWilliam.Wang@arm.com return; 91210037SARM gem5 Developers 91310037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 91410037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 91510037SARM gem5 Developers return; 91610037SARM gem5 Developers 9177408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 9187408Sgblack@eecs.umich.edu { 9197408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 9207408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 9217408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 9227408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 9237408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 9247408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 9257408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 9267408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 92710037SARM gem5 Developers fpscrMask.ioe = ones; 92810037SARM gem5 Developers fpscrMask.dze = ones; 92910037SARM gem5 Developers fpscrMask.ofe = ones; 93010037SARM gem5 Developers fpscrMask.ufe = ones; 93110037SARM gem5 Developers fpscrMask.ixe = ones; 93210037SARM gem5 Developers fpscrMask.ide = ones; 9337408Sgblack@eecs.umich.edu fpscrMask.len = ones; 93413759Sgiacomo.gabrielli@arm.com fpscrMask.fz16 = ones; 9357408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 9367408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 9377408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 9387408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 9397408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 9407408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 9417408Sgblack@eecs.umich.edu fpscrMask.v = ones; 9427408Sgblack@eecs.umich.edu fpscrMask.c = ones; 9437408Sgblack@eecs.umich.edu fpscrMask.z = ones; 9447408Sgblack@eecs.umich.edu fpscrMask.n = ones; 9457408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 94610037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 94710037SARM gem5 Developers ~(uint32_t)fpscrMask); 9489377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 9497408Sgblack@eecs.umich.edu } 9507408Sgblack@eecs.umich.edu break; 95110037SARM gem5 Developers case MISCREG_FPSR: 95210037SARM gem5 Developers { 95310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 95410037SARM gem5 Developers FPSCR fpscrMask = 0; 95510037SARM gem5 Developers fpscrMask.ioc = ones; 95610037SARM gem5 Developers fpscrMask.dzc = ones; 95710037SARM gem5 Developers fpscrMask.ofc = ones; 95810037SARM gem5 Developers fpscrMask.ufc = ones; 95910037SARM gem5 Developers fpscrMask.ixc = ones; 96010037SARM gem5 Developers fpscrMask.idc = ones; 96110037SARM gem5 Developers fpscrMask.qc = ones; 96210037SARM gem5 Developers fpscrMask.v = ones; 96310037SARM gem5 Developers fpscrMask.c = ones; 96410037SARM gem5 Developers fpscrMask.z = ones; 96510037SARM gem5 Developers fpscrMask.n = ones; 96610037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 96710037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 96810037SARM gem5 Developers ~(uint32_t)fpscrMask); 96910037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 97010037SARM gem5 Developers } 97110037SARM gem5 Developers break; 97210037SARM gem5 Developers case MISCREG_FPCR: 97310037SARM gem5 Developers { 97410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 97510037SARM gem5 Developers FPSCR fpscrMask = 0; 97610037SARM gem5 Developers fpscrMask.len = ones; 97713759Sgiacomo.gabrielli@arm.com fpscrMask.fz16 = ones; 97810037SARM gem5 Developers fpscrMask.stride = ones; 97910037SARM gem5 Developers fpscrMask.rMode = ones; 98010037SARM gem5 Developers fpscrMask.fz = ones; 98110037SARM gem5 Developers fpscrMask.dn = ones; 98210037SARM gem5 Developers fpscrMask.ahp = ones; 98310037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 98410037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 98510037SARM gem5 Developers ~(uint32_t)fpscrMask); 98610037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 98710037SARM gem5 Developers } 98810037SARM gem5 Developers break; 9898302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 9908302SAli.Saidi@ARM.com { 9918302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 99210037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 9938302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 9948302SAli.Saidi@ARM.com } 9958302SAli.Saidi@ARM.com break; 9967783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 9977783SGiacomo.Gabrielli@arm.com { 99810037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 99910037SARM gem5 Developers (newVal & FpscrQcMask); 10007783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 10017783SGiacomo.Gabrielli@arm.com } 10027783SGiacomo.Gabrielli@arm.com break; 10037783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 10047783SGiacomo.Gabrielli@arm.com { 100510037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 100610037SARM gem5 Developers (newVal & FpscrExcMask); 10077783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 10087783SGiacomo.Gabrielli@arm.com } 10097783SGiacomo.Gabrielli@arm.com break; 10107408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 10117408Sgblack@eecs.umich.edu { 10128206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 10138206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 10147408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 10157408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 101610037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 10177408Sgblack@eecs.umich.edu } 10187408Sgblack@eecs.umich.edu break; 101910037SARM gem5 Developers case MISCREG_HCR: 102010037SARM gem5 Developers { 102110037SARM gem5 Developers if (!haveVirtualization) 102210037SARM gem5 Developers return; 102310037SARM gem5 Developers } 102410037SARM gem5 Developers break; 102510037SARM gem5 Developers case MISCREG_IFSR: 102610037SARM gem5 Developers { 102710037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 102810037SARM gem5 Developers const uint32_t ifsrMask = 102910037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 103010037SARM gem5 Developers newVal = newVal & ~ifsrMask; 103110037SARM gem5 Developers } 103210037SARM gem5 Developers break; 103310037SARM gem5 Developers case MISCREG_DFSR: 103410037SARM gem5 Developers { 103510037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 103610037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 103710037SARM gem5 Developers newVal = newVal & ~dfsrMask; 103810037SARM gem5 Developers } 103910037SARM gem5 Developers break; 104010037SARM gem5 Developers case MISCREG_AMAIR0: 104110037SARM gem5 Developers case MISCREG_AMAIR1: 104210037SARM gem5 Developers { 104310037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 104410037SARM gem5 Developers // Valid only with LPAE 104510037SARM gem5 Developers if (!haveLPAE) 104610037SARM gem5 Developers return; 104710037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 104810037SARM gem5 Developers } 104910037SARM gem5 Developers break; 105010037SARM gem5 Developers case MISCREG_SCR: 105112406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 105212406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 105310037SARM gem5 Developers break; 10547408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 10557408Sgblack@eecs.umich.edu { 10567408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 105710037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 105812639Sgiacomo.travaglini@arm.com 105912639Sgiacomo.travaglini@arm.com MiscRegIndex sctlr_idx; 106012639Sgiacomo.travaglini@arm.com if (haveSecurity && !highestELIs64 && !scr.ns) { 106112639Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_S; 106212639Sgiacomo.travaglini@arm.com } else { 106312639Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_NS; 106412639Sgiacomo.travaglini@arm.com } 106512639Sgiacomo.travaglini@arm.com 106610037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 10677408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 106810037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 106913581Sgabeblack@google.com miscRegs[sctlr_idx] = (RegVal)new_sctlr; 107012406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 107112406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 10727408Sgblack@eecs.umich.edu } 10739385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 10749385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 10759385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 107610461SAndreas.Sandberg@ARM.com case MISCREG_ID_DFR0: 10779385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 10789385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 10799385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 10809385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 10819385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 10829385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 10839385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 10849385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 10859385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 10869385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 10879385SAndreas.Sandberg@arm.com 10889385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 10899385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 10907408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 10917408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 10927408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 109310037SARM gem5 Developers 109410037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 109510037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 109610037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 109710037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 109810037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 109910037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 110010037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 110110037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 110213116Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR2_EL1: 110310037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 110410037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 11059385SAndreas.Sandberg@arm.com // ID registers are constants. 11067408Sgblack@eecs.umich.edu return; 11079385SAndreas.Sandberg@arm.com 110812605Sgiacomo.travaglini@arm.com // TLB Invalidate All 110912605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 111012605Sgiacomo.travaglini@arm.com { 111112605Sgiacomo.travaglini@arm.com assert32(tc); 111212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 111312605Sgiacomo.travaglini@arm.com 111412605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 111512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 111612605Sgiacomo.travaglini@arm.com return; 111712605Sgiacomo.travaglini@arm.com } 111812605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Inner Shareable 11197408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 112012605Sgiacomo.travaglini@arm.com { 112112605Sgiacomo.travaglini@arm.com assert32(tc); 112212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 112312605Sgiacomo.travaglini@arm.com 112412605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 112512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 112612605Sgiacomo.travaglini@arm.com return; 112712605Sgiacomo.travaglini@arm.com } 112812605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate All 11297408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 113012605Sgiacomo.travaglini@arm.com { 113112605Sgiacomo.travaglini@arm.com assert32(tc); 113212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 113312605Sgiacomo.travaglini@arm.com 113412605Sgiacomo.travaglini@arm.com ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 113512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 113612605Sgiacomo.travaglini@arm.com return; 113712605Sgiacomo.travaglini@arm.com } 113812605Sgiacomo.travaglini@arm.com // Data TLB Invalidate All 11397408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 114012605Sgiacomo.travaglini@arm.com { 114112605Sgiacomo.travaglini@arm.com assert32(tc); 114212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 114312605Sgiacomo.travaglini@arm.com 114412605Sgiacomo.travaglini@arm.com DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 114512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 114612605Sgiacomo.travaglini@arm.com return; 114712605Sgiacomo.travaglini@arm.com } 114812605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA 114912605Sgiacomo.travaglini@arm.com // mcr tlbimval(is) is invalidating all matching entries 115012605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 115112605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 115212605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVA: 115312576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAL: 115412605Sgiacomo.travaglini@arm.com { 115512605Sgiacomo.travaglini@arm.com assert32(tc); 115612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 115712605Sgiacomo.travaglini@arm.com 115812605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 115912605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 116012605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 116112605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 116212605Sgiacomo.travaglini@arm.com 116312605Sgiacomo.travaglini@arm.com tlbiOp(tc); 116412605Sgiacomo.travaglini@arm.com return; 116512605Sgiacomo.travaglini@arm.com } 116612605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Inner Shareable 116712605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAIS: 116812576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALIS: 116912605Sgiacomo.travaglini@arm.com { 117012605Sgiacomo.travaglini@arm.com assert32(tc); 117112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 117212605Sgiacomo.travaglini@arm.com 117312605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 117412605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 117512605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 117612605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 117712605Sgiacomo.travaglini@arm.com 117812605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 117912605Sgiacomo.travaglini@arm.com return; 118012605Sgiacomo.travaglini@arm.com } 118112605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match 118212605Sgiacomo.travaglini@arm.com case MISCREG_TLBIASID: 118312605Sgiacomo.travaglini@arm.com { 118412605Sgiacomo.travaglini@arm.com assert32(tc); 118512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 118612605Sgiacomo.travaglini@arm.com 118712605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 118812605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 118912605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 119012605Sgiacomo.travaglini@arm.com 119112605Sgiacomo.travaglini@arm.com tlbiOp(tc); 119212605Sgiacomo.travaglini@arm.com return; 119312605Sgiacomo.travaglini@arm.com } 119412605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match, Inner Shareable 11957408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 119612605Sgiacomo.travaglini@arm.com { 119712605Sgiacomo.travaglini@arm.com assert32(tc); 119812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 119912605Sgiacomo.travaglini@arm.com 120012605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 120112605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 120212605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 120312605Sgiacomo.travaglini@arm.com 120412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 120512605Sgiacomo.travaglini@arm.com return; 120612605Sgiacomo.travaglini@arm.com } 120712605Sgiacomo.travaglini@arm.com // mcr tlbimvaal(is) is invalidating all matching entries 120812605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 120912605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 121012605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID 121112605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAA: 121212576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAL: 121312605Sgiacomo.travaglini@arm.com { 121412605Sgiacomo.travaglini@arm.com assert32(tc); 121512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 121612605Sgiacomo.travaglini@arm.com 121712605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 121813882Sgiacomo.travaglini@arm.com mbits(newVal, 31,12)); 121912605Sgiacomo.travaglini@arm.com 122012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 122112605Sgiacomo.travaglini@arm.com return; 122212605Sgiacomo.travaglini@arm.com } 122312605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID, Inner Shareable 122412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAIS: 122512576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAALIS: 122612605Sgiacomo.travaglini@arm.com { 122712605Sgiacomo.travaglini@arm.com assert32(tc); 122812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 122912605Sgiacomo.travaglini@arm.com 123012605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 123113882Sgiacomo.travaglini@arm.com mbits(newVal, 31,12)); 123212605Sgiacomo.travaglini@arm.com 123312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 123412605Sgiacomo.travaglini@arm.com return; 123512605Sgiacomo.travaglini@arm.com } 123612605Sgiacomo.travaglini@arm.com // mcr tlbimvalh(is) is invalidating all matching entries 123712605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 123812605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 123912605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode 124012605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAH: 124112576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALH: 124212605Sgiacomo.travaglini@arm.com { 124312605Sgiacomo.travaglini@arm.com assert32(tc); 124412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 124512605Sgiacomo.travaglini@arm.com 124613881Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 124713882Sgiacomo.travaglini@arm.com mbits(newVal, 31,12)); 124812605Sgiacomo.travaglini@arm.com 124912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 125012605Sgiacomo.travaglini@arm.com return; 125112605Sgiacomo.travaglini@arm.com } 125212605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode, Inner Shareable 125312605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAHIS: 125412576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALHIS: 125512605Sgiacomo.travaglini@arm.com { 125612605Sgiacomo.travaglini@arm.com assert32(tc); 125712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 125812605Sgiacomo.travaglini@arm.com 125913881Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 126013882Sgiacomo.travaglini@arm.com mbits(newVal, 31,12)); 126112605Sgiacomo.travaglini@arm.com 126212605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 126312605Sgiacomo.travaglini@arm.com return; 126412605Sgiacomo.travaglini@arm.com } 126512605Sgiacomo.travaglini@arm.com // mcr tlbiipas2l(is) is invalidating all matching entries 126612605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 126712605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 126812605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2 126912605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2: 127012577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2L: 127112605Sgiacomo.travaglini@arm.com { 127212605Sgiacomo.travaglini@arm.com assert32(tc); 127312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 127412605Sgiacomo.travaglini@arm.com 127512605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 127612605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 127712605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 127812605Sgiacomo.travaglini@arm.com 127912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 128012605Sgiacomo.travaglini@arm.com return; 128112605Sgiacomo.travaglini@arm.com } 128212605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2, 128312605Sgiacomo.travaglini@arm.com // Inner Shareable 128412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2IS: 128512577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2LIS: 128612605Sgiacomo.travaglini@arm.com { 128712605Sgiacomo.travaglini@arm.com assert32(tc); 128812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 128912605Sgiacomo.travaglini@arm.com 129012605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 129112605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 129212605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 129312605Sgiacomo.travaglini@arm.com 129412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 129512605Sgiacomo.travaglini@arm.com return; 129612605Sgiacomo.travaglini@arm.com } 129712605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by VA 129810037SARM gem5 Developers case MISCREG_ITLBIMVA: 129912605Sgiacomo.travaglini@arm.com { 130012605Sgiacomo.travaglini@arm.com assert32(tc); 130112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 130212605Sgiacomo.travaglini@arm.com 130312605Sgiacomo.travaglini@arm.com ITLBIMVA tlbiOp(EL1, 130412605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 130512605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 130612605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 130712605Sgiacomo.travaglini@arm.com 130812605Sgiacomo.travaglini@arm.com tlbiOp(tc); 130912605Sgiacomo.travaglini@arm.com return; 131012605Sgiacomo.travaglini@arm.com } 131112605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by VA 131210037SARM gem5 Developers case MISCREG_DTLBIMVA: 131312605Sgiacomo.travaglini@arm.com { 131412605Sgiacomo.travaglini@arm.com assert32(tc); 131512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 131612605Sgiacomo.travaglini@arm.com 131712605Sgiacomo.travaglini@arm.com DTLBIMVA tlbiOp(EL1, 131812605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 131912605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 132012605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 132112605Sgiacomo.travaglini@arm.com 132212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 132312605Sgiacomo.travaglini@arm.com return; 132412605Sgiacomo.travaglini@arm.com } 132512605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by ASID match 132610037SARM gem5 Developers case MISCREG_ITLBIASID: 132712605Sgiacomo.travaglini@arm.com { 132812605Sgiacomo.travaglini@arm.com assert32(tc); 132912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 133012605Sgiacomo.travaglini@arm.com 133112605Sgiacomo.travaglini@arm.com ITLBIASID tlbiOp(EL1, 133212605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 133312605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 133412605Sgiacomo.travaglini@arm.com 133512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 133612605Sgiacomo.travaglini@arm.com return; 133712605Sgiacomo.travaglini@arm.com } 133812605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by ASID match 133910037SARM gem5 Developers case MISCREG_DTLBIASID: 134012605Sgiacomo.travaglini@arm.com { 134112605Sgiacomo.travaglini@arm.com assert32(tc); 134212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 134312605Sgiacomo.travaglini@arm.com 134412605Sgiacomo.travaglini@arm.com DTLBIASID tlbiOp(EL1, 134512605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 134612605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 134712605Sgiacomo.travaglini@arm.com 134812605Sgiacomo.travaglini@arm.com tlbiOp(tc); 134912605Sgiacomo.travaglini@arm.com return; 135012605Sgiacomo.travaglini@arm.com } 135112605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp 135210037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 135312605Sgiacomo.travaglini@arm.com { 135412605Sgiacomo.travaglini@arm.com assert32(tc); 135512605Sgiacomo.travaglini@arm.com 135613882Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1); 135712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 135812605Sgiacomo.travaglini@arm.com return; 135912605Sgiacomo.travaglini@arm.com } 136012605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 136110037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 136212605Sgiacomo.travaglini@arm.com { 136312605Sgiacomo.travaglini@arm.com assert32(tc); 136412605Sgiacomo.travaglini@arm.com 136513882Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1); 136612605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 136712605Sgiacomo.travaglini@arm.com return; 136812605Sgiacomo.travaglini@arm.com } 136912605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode 137010037SARM gem5 Developers case MISCREG_TLBIALLH: 137112605Sgiacomo.travaglini@arm.com { 137212605Sgiacomo.travaglini@arm.com assert32(tc); 137312605Sgiacomo.travaglini@arm.com 137413882Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL2); 137512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 137612605Sgiacomo.travaglini@arm.com return; 137712605Sgiacomo.travaglini@arm.com } 137812605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode, Inner Shareable 137910037SARM gem5 Developers case MISCREG_TLBIALLHIS: 138012605Sgiacomo.travaglini@arm.com { 138112605Sgiacomo.travaglini@arm.com assert32(tc); 138212605Sgiacomo.travaglini@arm.com 138313882Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL2); 138412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 138512605Sgiacomo.travaglini@arm.com return; 138612605Sgiacomo.travaglini@arm.com } 138712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3 138812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE3: 138912605Sgiacomo.travaglini@arm.com { 139012605Sgiacomo.travaglini@arm.com assert64(tc); 139112605Sgiacomo.travaglini@arm.com 139212605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 139312605Sgiacomo.travaglini@arm.com tlbiOp(tc); 139412605Sgiacomo.travaglini@arm.com return; 139512605Sgiacomo.travaglini@arm.com } 139612605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3, Inner Shareable 139710037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 139812605Sgiacomo.travaglini@arm.com { 139912605Sgiacomo.travaglini@arm.com assert64(tc); 140012605Sgiacomo.travaglini@arm.com 140112605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 140212605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 140312605Sgiacomo.travaglini@arm.com return; 140412605Sgiacomo.travaglini@arm.com } 140513549Sanouk.vanlaer@arm.com // AArch64 TLB Invalidate All, EL2, Inner Shareable 140613549Sanouk.vanlaer@arm.com case MISCREG_TLBI_ALLE2: 140713549Sanouk.vanlaer@arm.com case MISCREG_TLBI_ALLE2IS: 140813549Sanouk.vanlaer@arm.com { 140913549Sanouk.vanlaer@arm.com assert64(tc); 141013549Sanouk.vanlaer@arm.com scr = readMiscReg(MISCREG_SCR, tc); 141113549Sanouk.vanlaer@arm.com 141213549Sanouk.vanlaer@arm.com TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 141313549Sanouk.vanlaer@arm.com tlbiOp(tc); 141413549Sanouk.vanlaer@arm.com return; 141513549Sanouk.vanlaer@arm.com } 141612605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1 141710037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 141810037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 141910037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 142010037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 142112605Sgiacomo.travaglini@arm.com { 142212605Sgiacomo.travaglini@arm.com assert64(tc); 142312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 142412605Sgiacomo.travaglini@arm.com 142512605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 142612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 142712605Sgiacomo.travaglini@arm.com return; 142812605Sgiacomo.travaglini@arm.com } 142912605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1, Inner Shareable 143012605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE1IS: 143112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLE1IS: 143212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLS12E1IS: 143312605Sgiacomo.travaglini@arm.com // @todo: handle VMID and stage 2 to enable Virtualization 143412605Sgiacomo.travaglini@arm.com { 143512605Sgiacomo.travaglini@arm.com assert64(tc); 143612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 143712605Sgiacomo.travaglini@arm.com 143812605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 143912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 144012605Sgiacomo.travaglini@arm.com return; 144112605Sgiacomo.travaglini@arm.com } 144212605Sgiacomo.travaglini@arm.com // VAEx(IS) and VALEx(IS) are the same because TLBs 144312605Sgiacomo.travaglini@arm.com // only store entries 144410037SARM gem5 Developers // from the last level of translation table walks 144510037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 144612605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3 144712605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE3_Xt: 144812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE3_Xt: 144912605Sgiacomo.travaglini@arm.com { 145012605Sgiacomo.travaglini@arm.com assert64(tc); 145112605Sgiacomo.travaglini@arm.com 145212605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 145312605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 145412605Sgiacomo.travaglini@arm.com 0xbeef); 145512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 145612605Sgiacomo.travaglini@arm.com return; 145712605Sgiacomo.travaglini@arm.com } 145812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 145910037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 146010037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 146112605Sgiacomo.travaglini@arm.com { 146212605Sgiacomo.travaglini@arm.com assert64(tc); 146312605Sgiacomo.travaglini@arm.com 146412605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 146512605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 146612605Sgiacomo.travaglini@arm.com 0xbeef); 146712605Sgiacomo.travaglini@arm.com 146812605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 146912605Sgiacomo.travaglini@arm.com return; 147012605Sgiacomo.travaglini@arm.com } 147112605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2 147212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE2_Xt: 147312605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE2_Xt: 147412605Sgiacomo.travaglini@arm.com { 147512605Sgiacomo.travaglini@arm.com assert64(tc); 147612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 147712605Sgiacomo.travaglini@arm.com 147812605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 147912605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 148012605Sgiacomo.travaglini@arm.com 0xbeef); 148112605Sgiacomo.travaglini@arm.com tlbiOp(tc); 148212605Sgiacomo.travaglini@arm.com return; 148312605Sgiacomo.travaglini@arm.com } 148412605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 148510037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 148610037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 148712605Sgiacomo.travaglini@arm.com { 148812605Sgiacomo.travaglini@arm.com assert64(tc); 148912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 149012605Sgiacomo.travaglini@arm.com 149112605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 149212605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 149312605Sgiacomo.travaglini@arm.com 0xbeef); 149412605Sgiacomo.travaglini@arm.com 149512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 149612605Sgiacomo.travaglini@arm.com return; 149712605Sgiacomo.travaglini@arm.com } 149812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1 149912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1_Xt: 150012605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE1_Xt: 150112605Sgiacomo.travaglini@arm.com { 150212605Sgiacomo.travaglini@arm.com assert64(tc); 150312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 150412605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 150512605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 150612605Sgiacomo.travaglini@arm.com 150712605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 150812605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 150912605Sgiacomo.travaglini@arm.com asid); 151012605Sgiacomo.travaglini@arm.com 151112605Sgiacomo.travaglini@arm.com tlbiOp(tc); 151212605Sgiacomo.travaglini@arm.com return; 151312605Sgiacomo.travaglini@arm.com } 151412605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 151510037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 151610037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 151712605Sgiacomo.travaglini@arm.com { 151812605Sgiacomo.travaglini@arm.com assert64(tc); 151912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 152012605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 152112605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 152212605Sgiacomo.travaglini@arm.com 152312605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 152412605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 152512605Sgiacomo.travaglini@arm.com asid); 152612605Sgiacomo.travaglini@arm.com 152712605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 152812605Sgiacomo.travaglini@arm.com return; 152912605Sgiacomo.travaglini@arm.com } 153012605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1 153110037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 153212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ASIDE1_Xt: 153312605Sgiacomo.travaglini@arm.com { 153412605Sgiacomo.travaglini@arm.com assert64(tc); 153512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 153612605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 153712605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 153812605Sgiacomo.travaglini@arm.com 153912605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 154012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 154112605Sgiacomo.travaglini@arm.com return; 154212605Sgiacomo.travaglini@arm.com } 154312605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 154410037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 154512605Sgiacomo.travaglini@arm.com { 154612605Sgiacomo.travaglini@arm.com assert64(tc); 154712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 154812605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 154912605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 155012605Sgiacomo.travaglini@arm.com 155112605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 155212605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 155312605Sgiacomo.travaglini@arm.com return; 155412605Sgiacomo.travaglini@arm.com } 155510037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 155610037SARM gem5 Developers // entries from the last level of translation table walks 155712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1 155812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAAE1_Xt: 155912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAALE1_Xt: 156012605Sgiacomo.travaglini@arm.com { 156112605Sgiacomo.travaglini@arm.com assert64(tc); 156212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 156312605Sgiacomo.travaglini@arm.com 156412605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 156513882Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12); 156612605Sgiacomo.travaglini@arm.com 156712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 156812605Sgiacomo.travaglini@arm.com return; 156912605Sgiacomo.travaglini@arm.com } 157012605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 157110037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 157210037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 157312605Sgiacomo.travaglini@arm.com { 157412605Sgiacomo.travaglini@arm.com assert64(tc); 157512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 157612605Sgiacomo.travaglini@arm.com 157712605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 157813882Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12); 157912605Sgiacomo.travaglini@arm.com 158012605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 158112605Sgiacomo.travaglini@arm.com return; 158212605Sgiacomo.travaglini@arm.com } 158312605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 158412605Sgiacomo.travaglini@arm.com // Stage 2, EL1 158512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1_Xt: 158612605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2LE1_Xt: 158712605Sgiacomo.travaglini@arm.com { 158812605Sgiacomo.travaglini@arm.com assert64(tc); 158912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 159012605Sgiacomo.travaglini@arm.com 159112605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 159212605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 159312605Sgiacomo.travaglini@arm.com 159412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 159512605Sgiacomo.travaglini@arm.com return; 159612605Sgiacomo.travaglini@arm.com } 159712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 159812605Sgiacomo.travaglini@arm.com // Stage 2, EL1, Inner Shareable 159912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1IS_Xt: 160010037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 160112605Sgiacomo.travaglini@arm.com { 160212605Sgiacomo.travaglini@arm.com assert64(tc); 160312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 160412605Sgiacomo.travaglini@arm.com 160512605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 160612605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 160712605Sgiacomo.travaglini@arm.com 160812605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 160912605Sgiacomo.travaglini@arm.com return; 161012605Sgiacomo.travaglini@arm.com } 16117583SAli.Saidi@arm.com case MISCREG_ACTLR: 16127583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 16137583SAli.Saidi@arm.com break; 161410461SAndreas.Sandberg@ARM.com 161510461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 161610461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 161710461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 161810461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 161910461SAndreas.Sandberg@ARM.com pmu->setMiscReg(misc_reg, newVal); 16207583SAli.Saidi@arm.com break; 162110461SAndreas.Sandberg@ARM.com 162210461SAndreas.Sandberg@ARM.com 162310037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 162410037SARM gem5 Developers { 162510037SARM gem5 Developers HSTR hstrMask = 0; 162610037SARM gem5 Developers hstrMask.tjdbx = 1; 162710037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 162810037SARM gem5 Developers break; 162910037SARM gem5 Developers } 163010037SARM gem5 Developers case MISCREG_HCPTR: 163110037SARM gem5 Developers { 163210037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 163310037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 163410037SARM gem5 Developers secure_lookup = haveSecurity && 163510037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 163610037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 163710037SARM gem5 Developers if (!secure_lookup) { 163813581Sgabeblack@google.com RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 163913581Sgabeblack@google.com RegVal mask = 164013581Sgabeblack@google.com (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 164110037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 164210037SARM gem5 Developers } 164310037SARM gem5 Developers break; 164410037SARM gem5 Developers } 164510037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 164610037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 164710037SARM gem5 Developers break; 164810037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 164910037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 165010037SARM gem5 Developers break; 165110037SARM gem5 Developers case MISCREG_ATS1CPR: 165210037SARM gem5 Developers case MISCREG_ATS1CPW: 165310037SARM gem5 Developers case MISCREG_ATS1CUR: 165410037SARM gem5 Developers case MISCREG_ATS1CUW: 165510037SARM gem5 Developers case MISCREG_ATS12NSOPR: 165610037SARM gem5 Developers case MISCREG_ATS12NSOPW: 165710037SARM gem5 Developers case MISCREG_ATS12NSOUR: 165810037SARM gem5 Developers case MISCREG_ATS12NSOUW: 165910037SARM gem5 Developers case MISCREG_ATS1HR: 166010037SARM gem5 Developers case MISCREG_ATS1HW: 16617436Sdam.sunwoo@arm.com { 166211608Snikos.nikoleris@arm.com Request::Flags flags = 0; 166310037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 166410037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 16657436Sdam.sunwoo@arm.com Fault fault; 16667436Sdam.sunwoo@arm.com switch(misc_reg) { 166710037SARM gem5 Developers case MISCREG_ATS1CPR: 166810037SARM gem5 Developers flags = TLB::MustBeOne; 166910037SARM gem5 Developers tranType = TLB::S1CTran; 167010037SARM gem5 Developers mode = BaseTLB::Read; 167110037SARM gem5 Developers break; 167210037SARM gem5 Developers case MISCREG_ATS1CPW: 167310037SARM gem5 Developers flags = TLB::MustBeOne; 167410037SARM gem5 Developers tranType = TLB::S1CTran; 167510037SARM gem5 Developers mode = BaseTLB::Write; 167610037SARM gem5 Developers break; 167710037SARM gem5 Developers case MISCREG_ATS1CUR: 167810037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 167910037SARM gem5 Developers tranType = TLB::S1CTran; 168010037SARM gem5 Developers mode = BaseTLB::Read; 168110037SARM gem5 Developers break; 168210037SARM gem5 Developers case MISCREG_ATS1CUW: 168310037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 168410037SARM gem5 Developers tranType = TLB::S1CTran; 168510037SARM gem5 Developers mode = BaseTLB::Write; 168610037SARM gem5 Developers break; 168710037SARM gem5 Developers case MISCREG_ATS12NSOPR: 168810037SARM gem5 Developers if (!haveSecurity) 168910037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 169010037SARM gem5 Developers flags = TLB::MustBeOne; 169110037SARM gem5 Developers tranType = TLB::S1S2NsTran; 169210037SARM gem5 Developers mode = BaseTLB::Read; 169310037SARM gem5 Developers break; 169410037SARM gem5 Developers case MISCREG_ATS12NSOPW: 169510037SARM gem5 Developers if (!haveSecurity) 169610037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 169710037SARM gem5 Developers flags = TLB::MustBeOne; 169810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 169910037SARM gem5 Developers mode = BaseTLB::Write; 170010037SARM gem5 Developers break; 170110037SARM gem5 Developers case MISCREG_ATS12NSOUR: 170210037SARM gem5 Developers if (!haveSecurity) 170310037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 170410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 170510037SARM gem5 Developers tranType = TLB::S1S2NsTran; 170610037SARM gem5 Developers mode = BaseTLB::Read; 170710037SARM gem5 Developers break; 170810037SARM gem5 Developers case MISCREG_ATS12NSOUW: 170910037SARM gem5 Developers if (!haveSecurity) 171010037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 171110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 171210037SARM gem5 Developers tranType = TLB::S1S2NsTran; 171310037SARM gem5 Developers mode = BaseTLB::Write; 171410037SARM gem5 Developers break; 171510037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 171610037SARM gem5 Developers flags = TLB::MustBeOne; 171710037SARM gem5 Developers tranType = TLB::HypMode; 171810037SARM gem5 Developers mode = BaseTLB::Read; 171910037SARM gem5 Developers break; 172010037SARM gem5 Developers case MISCREG_ATS1HW: 172110037SARM gem5 Developers flags = TLB::MustBeOne; 172210037SARM gem5 Developers tranType = TLB::HypMode; 172310037SARM gem5 Developers mode = BaseTLB::Write; 172410037SARM gem5 Developers break; 17257436Sdam.sunwoo@arm.com } 172610037SARM gem5 Developers // If we're in timing mode then doing the translation in 172710037SARM gem5 Developers // functional mode then we're slightly distorting performance 172810037SARM gem5 Developers // results obtained from simulations. The translation should be 172910037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 173010037SARM gem5 Developers // can't be an atomic translation because that causes problems 173110037SARM gem5 Developers // with unexpected atomic snoop requests. 173213417Sgiacomo.travaglini@arm.com warn("Translating via %s in functional mode! Fix Me!\n", 173313417Sgiacomo.travaglini@arm.com miscRegName[misc_reg]); 173412749Sgiacomo.travaglini@arm.com 173512749Sgiacomo.travaglini@arm.com auto req = std::make_shared<Request>( 173612749Sgiacomo.travaglini@arm.com 0, val, 0, flags, Request::funcMasterId, 173712749Sgiacomo.travaglini@arm.com tc->pcState().pc(), tc->contextId()); 173812749Sgiacomo.travaglini@arm.com 173912406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional( 174012749Sgiacomo.travaglini@arm.com req, tc, mode, tranType); 174112749Sgiacomo.travaglini@arm.com 174210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 174310037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 174410037SARM gem5 Developers 174513581Sgabeblack@google.com RegVal newVal; 17467436Sdam.sunwoo@arm.com if (fault == NoFault) { 174712749Sgiacomo.travaglini@arm.com Addr paddr = req->getPaddr(); 174810037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 174910037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 175010037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 175112406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 175210037SARM gem5 Developers } else { 175310037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 175412406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 175510037SARM gem5 Developers } 17567436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 17577436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 175810037SARM gem5 Developers val, newVal); 175910037SARM gem5 Developers } else { 176012524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 176112570Sgiacomo.travaglini@arm.com armFault->update(tc); 176210037SARM gem5 Developers // Set fault bit and FSR 176310037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 176410037SARM gem5 Developers 176510037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 176610037SARM gem5 Developers if (newVal) { 176710037SARM gem5 Developers // LPAE - rearange fault status 176810037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 176910037SARM gem5 Developers } else { 177010037SARM gem5 Developers // VMSA - rearange fault status 177110037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 177210037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 177310037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 177410037SARM gem5 Developers } 177510037SARM gem5 Developers newVal |= 0x1; // F bit 177610037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 177710037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 177810037SARM gem5 Developers DPRINTF(MiscRegs, 177910037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 178010037SARM gem5 Developers val, fsr, newVal); 17817436Sdam.sunwoo@arm.com } 178210037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 17837436Sdam.sunwoo@arm.com return; 17847436Sdam.sunwoo@arm.com } 178510037SARM gem5 Developers case MISCREG_TTBCR: 178610037SARM gem5 Developers { 178710037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 178810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 178910037SARM gem5 Developers TTBCR ttbcrMask = 0; 179010037SARM gem5 Developers TTBCR ttbcrNew = newVal; 179110037SARM gem5 Developers 179210037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 179310037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 179410037SARM gem5 Developers if (haveSecurity) { 179510037SARM gem5 Developers ttbcrMask.pd0 = ones; 179610037SARM gem5 Developers ttbcrMask.pd1 = ones; 179710037SARM gem5 Developers } 179810037SARM gem5 Developers ttbcrMask.epd0 = ones; 179910037SARM gem5 Developers ttbcrMask.irgn0 = ones; 180010037SARM gem5 Developers ttbcrMask.orgn0 = ones; 180110037SARM gem5 Developers ttbcrMask.sh0 = ones; 180210037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 180310037SARM gem5 Developers ttbcrMask.a1 = ones; 180410037SARM gem5 Developers ttbcrMask.epd1 = ones; 180510037SARM gem5 Developers ttbcrMask.irgn1 = ones; 180610037SARM gem5 Developers ttbcrMask.orgn1 = ones; 180710037SARM gem5 Developers ttbcrMask.sh1 = ones; 180810037SARM gem5 Developers if (haveLPAE) 180910037SARM gem5 Developers ttbcrMask.eae = ones; 181010037SARM gem5 Developers 181110037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 181210037SARM gem5 Developers newVal = newVal & ttbcrMask; 181310037SARM gem5 Developers } else { 181410037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 181510037SARM gem5 Developers } 181612666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 181712666Sgiacomo.travaglini@arm.com getITBPtr(tc)->invalidateMiscReg(); 181812666Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 181912666Sgiacomo.travaglini@arm.com break; 182010037SARM gem5 Developers } 182110037SARM gem5 Developers case MISCREG_TTBR0: 182210037SARM gem5 Developers case MISCREG_TTBR1: 182310037SARM gem5 Developers { 182410037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 182510037SARM gem5 Developers if (haveLPAE) { 182610037SARM gem5 Developers if (ttbcr.eae) { 182710037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 182810037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 182910037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 183010037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 183110037SARM gem5 Developers } 183210037SARM gem5 Developers } 183312666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 183412406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 183512406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 183612666Sgiacomo.travaglini@arm.com break; 183710508SAli.Saidi@ARM.com } 183812666Sgiacomo.travaglini@arm.com case MISCREG_SCTLR_EL1: 18397749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 18407749SAli.Saidi@ARM.com case MISCREG_PRRR: 18417749SAli.Saidi@ARM.com case MISCREG_NMRR: 184210037SARM gem5 Developers case MISCREG_MAIR0: 184310037SARM gem5 Developers case MISCREG_MAIR1: 18447749SAli.Saidi@ARM.com case MISCREG_DACR: 184510037SARM gem5 Developers case MISCREG_VTTBR: 184610037SARM gem5 Developers case MISCREG_SCR_EL3: 184711575SDylan.Johnson@ARM.com case MISCREG_HCR_EL2: 184810037SARM gem5 Developers case MISCREG_TCR_EL1: 184910037SARM gem5 Developers case MISCREG_TCR_EL2: 185010037SARM gem5 Developers case MISCREG_TCR_EL3: 185110508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 185210508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 185311573SDylan.Johnson@ARM.com case MISCREG_HSCTLR: 185410037SARM gem5 Developers case MISCREG_TTBR0_EL1: 185510037SARM gem5 Developers case MISCREG_TTBR1_EL1: 185610037SARM gem5 Developers case MISCREG_TTBR0_EL2: 185712675Sgiacomo.travaglini@arm.com case MISCREG_TTBR1_EL2: 185810037SARM gem5 Developers case MISCREG_TTBR0_EL3: 185912406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 186012406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 18617749SAli.Saidi@ARM.com break; 186210037SARM gem5 Developers case MISCREG_NZCV: 186310037SARM gem5 Developers { 186410037SARM gem5 Developers CPSR cpsr = val; 186510037SARM gem5 Developers 186610338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_NZ, cpsr.nz); 186710338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_C, cpsr.c); 186810338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_V, cpsr.v); 186910037SARM gem5 Developers } 187010037SARM gem5 Developers break; 187110037SARM gem5 Developers case MISCREG_DAIF: 187210037SARM gem5 Developers { 187310037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 187410037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 187510037SARM gem5 Developers newVal = cpsr; 187610037SARM gem5 Developers misc_reg = MISCREG_CPSR; 187710037SARM gem5 Developers } 187810037SARM gem5 Developers break; 187910037SARM gem5 Developers case MISCREG_SP_EL0: 188010037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 188110037SARM gem5 Developers break; 188210037SARM gem5 Developers case MISCREG_SP_EL1: 188310037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 188410037SARM gem5 Developers break; 188510037SARM gem5 Developers case MISCREG_SP_EL2: 188610037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 188710037SARM gem5 Developers break; 188810037SARM gem5 Developers case MISCREG_SPSEL: 188910037SARM gem5 Developers { 189010037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 189110037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 189210037SARM gem5 Developers newVal = cpsr; 189310037SARM gem5 Developers misc_reg = MISCREG_CPSR; 189410037SARM gem5 Developers } 189510037SARM gem5 Developers break; 189610037SARM gem5 Developers case MISCREG_CURRENTEL: 189710037SARM gem5 Developers { 189810037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 189910037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 190010037SARM gem5 Developers newVal = cpsr; 190110037SARM gem5 Developers misc_reg = MISCREG_CPSR; 190210037SARM gem5 Developers } 190310037SARM gem5 Developers break; 190414128Sgiacomo.travaglini@arm.com case MISCREG_PAN: 190514128Sgiacomo.travaglini@arm.com { 190614128Sgiacomo.travaglini@arm.com // PAN is affecting data accesses 190714128Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 190814128Sgiacomo.travaglini@arm.com 190914128Sgiacomo.travaglini@arm.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 191014128Sgiacomo.travaglini@arm.com cpsr.pan = (uint8_t) ((CPSR) newVal).pan; 191114128Sgiacomo.travaglini@arm.com newVal = cpsr; 191214128Sgiacomo.travaglini@arm.com misc_reg = MISCREG_CPSR; 191314128Sgiacomo.travaglini@arm.com } 191414128Sgiacomo.travaglini@arm.com break; 191510037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 191610037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 191710037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 191810037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 191910037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 192010037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 192110037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 192210037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 192310037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 192410037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 192510037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 192610037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 192710037SARM gem5 Developers { 192812749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>(); 192911608Snikos.nikoleris@arm.com Request::Flags flags = 0; 193010037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 193110037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 193210037SARM gem5 Developers Fault fault; 193310037SARM gem5 Developers switch(misc_reg) { 193410037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 193510037SARM gem5 Developers flags = TLB::MustBeOne; 193611577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 193710037SARM gem5 Developers mode = BaseTLB::Read; 193810037SARM gem5 Developers break; 193910037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 194010037SARM gem5 Developers flags = TLB::MustBeOne; 194111577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 194210037SARM gem5 Developers mode = BaseTLB::Write; 194310037SARM gem5 Developers break; 194410037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 194510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 194611577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 194710037SARM gem5 Developers mode = BaseTLB::Read; 194810037SARM gem5 Developers break; 194910037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 195010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 195111577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 195210037SARM gem5 Developers mode = BaseTLB::Write; 195310037SARM gem5 Developers break; 195410037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 195510037SARM gem5 Developers flags = TLB::MustBeOne; 195611577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 195710037SARM gem5 Developers mode = BaseTLB::Read; 195810037SARM gem5 Developers break; 195910037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 196010037SARM gem5 Developers flags = TLB::MustBeOne; 196111577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 196210037SARM gem5 Developers mode = BaseTLB::Write; 196310037SARM gem5 Developers break; 196410037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 196510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 196611577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 196710037SARM gem5 Developers mode = BaseTLB::Read; 196810037SARM gem5 Developers break; 196910037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 197010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 197111577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 197210037SARM gem5 Developers mode = BaseTLB::Write; 197310037SARM gem5 Developers break; 197410037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 197510037SARM gem5 Developers flags = TLB::MustBeOne; 197611577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 197710037SARM gem5 Developers mode = BaseTLB::Read; 197810037SARM gem5 Developers break; 197910037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 198010037SARM gem5 Developers flags = TLB::MustBeOne; 198111577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 198210037SARM gem5 Developers mode = BaseTLB::Write; 198310037SARM gem5 Developers break; 198410037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 198510037SARM gem5 Developers flags = TLB::MustBeOne; 198611577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 198710037SARM gem5 Developers mode = BaseTLB::Read; 198810037SARM gem5 Developers break; 198910037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 199010037SARM gem5 Developers flags = TLB::MustBeOne; 199111577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 199210037SARM gem5 Developers mode = BaseTLB::Write; 199310037SARM gem5 Developers break; 199410037SARM gem5 Developers } 199510037SARM gem5 Developers // If we're in timing mode then doing the translation in 199610037SARM gem5 Developers // functional mode then we're slightly distorting performance 199710037SARM gem5 Developers // results obtained from simulations. The translation should be 199810037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 199910037SARM gem5 Developers // can't be an atomic translation because that causes problems 200010037SARM gem5 Developers // with unexpected atomic snoop requests. 200113417Sgiacomo.travaglini@arm.com warn("Translating via %s in functional mode! Fix Me!\n", 200213417Sgiacomo.travaglini@arm.com miscRegName[misc_reg]); 200313417Sgiacomo.travaglini@arm.com 200411560Sandreas.sandberg@arm.com req->setVirt(0, val, 0, flags, Request::funcMasterId, 200510037SARM gem5 Developers tc->pcState().pc()); 200611435Smitch.hayenga@arm.com req->setContext(tc->contextId()); 200712406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 200812406Sgabeblack@google.com tranType); 200910037SARM gem5 Developers 201013581Sgabeblack@google.com RegVal newVal; 201110037SARM gem5 Developers if (fault == NoFault) { 201210037SARM gem5 Developers Addr paddr = req->getPaddr(); 201312406Sgabeblack@google.com uint64_t attr = getDTBPtr(tc)->getAttr(); 201410037SARM gem5 Developers uint64_t attr1 = attr >> 56; 201510037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 201610037SARM gem5 Developers attr |= 0x100; 201710037SARM gem5 Developers attr &= ~ uint64_t(0x80); 201810037SARM gem5 Developers } 201910037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 202010037SARM gem5 Developers DPRINTF(MiscRegs, 202110037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 202210037SARM gem5 Developers val, newVal); 202310037SARM gem5 Developers } else { 202412524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 202512570Sgiacomo.travaglini@arm.com armFault->update(tc); 202610037SARM gem5 Developers // Set fault bit and FSR 202710037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 202810037SARM gem5 Developers 202911577SDylan.Johnson@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 203011577SDylan.Johnson@ARM.com if (cpsr.width) { // AArch32 203111577SDylan.Johnson@ARM.com newVal = ((fsr >> 9) & 1) << 11; 203211577SDylan.Johnson@ARM.com // rearrange fault status 203311577SDylan.Johnson@ARM.com newVal |= ((fsr >> 0) & 0x3f) << 1; 203411577SDylan.Johnson@ARM.com newVal |= 0x1; // F bit 203511577SDylan.Johnson@ARM.com newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 203611577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 0x200 : 0; 203711577SDylan.Johnson@ARM.com } else { // AArch64 203811577SDylan.Johnson@ARM.com newVal = 1; // F bit 203911577SDylan.Johnson@ARM.com newVal |= fsr << 1; // FST 204011577SDylan.Johnson@ARM.com // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 204111577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 204211577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 204311577SDylan.Johnson@ARM.com newVal |= 1 << 11; // RES1 204411577SDylan.Johnson@ARM.com } 204510037SARM gem5 Developers DPRINTF(MiscRegs, 204610037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 204710037SARM gem5 Developers val, fsr, newVal); 204810037SARM gem5 Developers } 204910037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 205010037SARM gem5 Developers return; 205110037SARM gem5 Developers } 205210037SARM gem5 Developers case MISCREG_SPSR_EL3: 205310037SARM gem5 Developers case MISCREG_SPSR_EL2: 205410037SARM gem5 Developers case MISCREG_SPSR_EL1: 205514128Sgiacomo.travaglini@arm.com { 205614128Sgiacomo.travaglini@arm.com RegVal spsr_mask = havePAN ? 205714128Sgiacomo.travaglini@arm.com ~(0x5 << 21) : ~(0x7 << 21); 205814128Sgiacomo.travaglini@arm.com 205914128Sgiacomo.travaglini@arm.com newVal = val & spsr_mask; 206014128Sgiacomo.travaglini@arm.com break; 206114128Sgiacomo.travaglini@arm.com } 20628549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 20638549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 20648549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 206510037SARM gem5 Developers break; 206610037SARM gem5 Developers 206710037SARM gem5 Developers // Generic Timer registers 206812816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CTL_EL2: 206912816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CVAL_EL2: 207012816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_TVAL_EL2: 207110844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 207210844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 207310844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 207410844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 207510844Sandreas.sandberg@arm.com getGenericTimer(tc).setMiscReg(misc_reg, newVal); 207610037SARM gem5 Developers break; 207714228Sgiacomo.travaglini@arm.com case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: 207813531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 207913531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 208013531Sjairo.balart@metempsy.com getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 208113531Sjairo.balart@metempsy.com return; 208213759Sgiacomo.gabrielli@arm.com case MISCREG_ZCR_EL3: 208313759Sgiacomo.gabrielli@arm.com case MISCREG_ZCR_EL2: 208413759Sgiacomo.gabrielli@arm.com case MISCREG_ZCR_EL1: 208513759Sgiacomo.gabrielli@arm.com tc->getDecoderPtr()->setSveLen( 208613759Sgiacomo.gabrielli@arm.com (getCurSveVecLenInBits(tc) >> 7) - 1); 208713759Sgiacomo.gabrielli@arm.com break; 20887405SAli.Saidi@ARM.com } 20897405SAli.Saidi@ARM.com } 20907405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 20917405SAli.Saidi@ARM.com} 20927405SAli.Saidi@ARM.com 209310844Sandreas.sandberg@arm.comBaseISADevice & 209410844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc) 209510037SARM gem5 Developers{ 209610844Sandreas.sandberg@arm.com // We only need to create an ISA interface the first time we try 209710844Sandreas.sandberg@arm.com // to access the timer. 209810844Sandreas.sandberg@arm.com if (timer) 209910844Sandreas.sandberg@arm.com return *timer.get(); 210010844Sandreas.sandberg@arm.com 210110844Sandreas.sandberg@arm.com assert(system); 210210844Sandreas.sandberg@arm.com GenericTimer *generic_timer(system->getGenericTimer()); 210310844Sandreas.sandberg@arm.com if (!generic_timer) { 210410844Sandreas.sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 210510844Sandreas.sandberg@arm.com "been configured to use a generic timer.\n"); 210610037SARM gem5 Developers } 210710037SARM gem5 Developers 210811150Smitch.hayenga@arm.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 210912972Sandreas.sandberg@arm.com timer->setThreadContext(tc); 211012972Sandreas.sandberg@arm.com 211110844Sandreas.sandberg@arm.com return *timer.get(); 211210037SARM gem5 Developers} 211310037SARM gem5 Developers 211413531Sjairo.balart@metempsy.comBaseISADevice & 211513531Sjairo.balart@metempsy.comISA::getGICv3CPUInterface(ThreadContext *tc) 211613531Sjairo.balart@metempsy.com{ 211713531Sjairo.balart@metempsy.com panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 211813531Sjairo.balart@metempsy.com return *gicv3CpuInterface.get(); 211913531Sjairo.balart@metempsy.com} 212013531Sjairo.balart@metempsy.com 212113759Sgiacomo.gabrielli@arm.comunsigned 212213759Sgiacomo.gabrielli@arm.comISA::getCurSveVecLenInBits(ThreadContext *tc) const 212313759Sgiacomo.gabrielli@arm.com{ 212413759Sgiacomo.gabrielli@arm.com if (!FullSystem) { 212513759Sgiacomo.gabrielli@arm.com return sveVL * 128; 212613759Sgiacomo.gabrielli@arm.com } 212713759Sgiacomo.gabrielli@arm.com 212813759Sgiacomo.gabrielli@arm.com panic_if(!tc, 212913759Sgiacomo.gabrielli@arm.com "A ThreadContext is needed to determine the SVE vector length " 213013759Sgiacomo.gabrielli@arm.com "in full-system mode"); 213113759Sgiacomo.gabrielli@arm.com 213213759Sgiacomo.gabrielli@arm.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 213313759Sgiacomo.gabrielli@arm.com ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 213413759Sgiacomo.gabrielli@arm.com 213513759Sgiacomo.gabrielli@arm.com unsigned len = 0; 213613759Sgiacomo.gabrielli@arm.com 213713759Sgiacomo.gabrielli@arm.com if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) { 213813759Sgiacomo.gabrielli@arm.com len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len; 213913759Sgiacomo.gabrielli@arm.com } 214013759Sgiacomo.gabrielli@arm.com 214113759Sgiacomo.gabrielli@arm.com if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) { 214213759Sgiacomo.gabrielli@arm.com len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len; 214313759Sgiacomo.gabrielli@arm.com } else if (haveVirtualization && !inSecureState(tc) && 214413759Sgiacomo.gabrielli@arm.com (el == EL0 || el == EL1)) { 214513759Sgiacomo.gabrielli@arm.com len = std::min( 214613759Sgiacomo.gabrielli@arm.com len, 214713759Sgiacomo.gabrielli@arm.com static_cast<unsigned>( 214813759Sgiacomo.gabrielli@arm.com static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len)); 214913759Sgiacomo.gabrielli@arm.com } 215013759Sgiacomo.gabrielli@arm.com 215113759Sgiacomo.gabrielli@arm.com if (el == EL3) { 215213759Sgiacomo.gabrielli@arm.com len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len; 215313759Sgiacomo.gabrielli@arm.com } else if (haveSecurity) { 215413759Sgiacomo.gabrielli@arm.com len = std::min( 215513759Sgiacomo.gabrielli@arm.com len, 215613759Sgiacomo.gabrielli@arm.com static_cast<unsigned>( 215713759Sgiacomo.gabrielli@arm.com static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len)); 215813759Sgiacomo.gabrielli@arm.com } 215913759Sgiacomo.gabrielli@arm.com 216013759Sgiacomo.gabrielli@arm.com len = std::min(len, sveVL - 1); 216113759Sgiacomo.gabrielli@arm.com 216213759Sgiacomo.gabrielli@arm.com return (len + 1) * 128; 21637405SAli.Saidi@ARM.com} 21649384SAndreas.Sandberg@arm.com 216513759Sgiacomo.gabrielli@arm.comvoid 216613759Sgiacomo.gabrielli@arm.comISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) 216713759Sgiacomo.gabrielli@arm.com{ 216813759Sgiacomo.gabrielli@arm.com auto vv = vc.as<uint64_t>(); 216913759Sgiacomo.gabrielli@arm.com for (int i = 2; i < eCount; ++i) { 217013759Sgiacomo.gabrielli@arm.com vv[i] = 0; 217113759Sgiacomo.gabrielli@arm.com } 217213759Sgiacomo.gabrielli@arm.com} 217313759Sgiacomo.gabrielli@arm.com 217413759Sgiacomo.gabrielli@arm.com} // namespace ArmISA 217513759Sgiacomo.gabrielli@arm.com 21769384SAndreas.Sandberg@arm.comArmISA::ISA * 21779384SAndreas.Sandberg@arm.comArmISAParams::create() 21789384SAndreas.Sandberg@arm.com{ 21799384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 21809384SAndreas.Sandberg@arm.com} 2181