12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 3310905Sandreas.sandberg@arm.com#include "arch/alpha/tlb.hh" 3410905Sandreas.sandberg@arm.com 3510905Sandreas.sandberg@arm.com#include <algorithm> 3610474Sandreas.hansson@arm.com#include <memory> 372SN/A#include <string> 382SN/A#include <vector> 392SN/A 408229Snate@binkert.org#include "arch/alpha/faults.hh" 412984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 428591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 43146SN/A#include "base/inifile.hh" 44146SN/A#include "base/str.hh" 45146SN/A#include "base/trace.hh" 462680Sktlim@umich.edu#include "cpu/thread_context.hh" 478232Snate@binkert.org#include "debug/TLB.hh" 488738Sgblack@eecs.umich.edu#include "sim/full_system.hh" 492SN/A 502SN/Ausing namespace std; 512SN/A 524088Sbinkertn@umich.edunamespace AlphaISA { 535569Snate@binkert.org 543838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 553838Shsul@eecs.umich.edu// 563838Shsul@eecs.umich.edu// Alpha TLB 573838Shsul@eecs.umich.edu// 585569Snate@binkert.org 59860SN/A#ifdef DEBUG 603838Shsul@eecs.umich.edubool uncacheBit39 = false; 613838Shsul@eecs.umich.edubool uncacheBit40 = false; 62860SN/A#endif 63860SN/A 645569Snate@binkert.org#define MODE2MASK(X) (1 << (X)) 651147SN/A 665034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 6710905Sandreas.sandberg@arm.com : BaseTLB(p), table(p->size), nlu(0) 683838Shsul@eecs.umich.edu{ 694957Sacolyte@umich.edu flushCache(); 703838Shsul@eecs.umich.edu} 712SN/A 723838Shsul@eecs.umich.eduTLB::~TLB() 733838Shsul@eecs.umich.edu{ 743838Shsul@eecs.umich.edu} 752SN/A 766022Sgblack@eecs.umich.eduvoid 776022Sgblack@eecs.umich.eduTLB::regStats() 786022Sgblack@eecs.umich.edu{ 7911523Sdavid.guillen@arm.com BaseTLB::regStats(); 8011523Sdavid.guillen@arm.com 816022Sgblack@eecs.umich.edu fetch_hits 826022Sgblack@eecs.umich.edu .name(name() + ".fetch_hits") 836022Sgblack@eecs.umich.edu .desc("ITB hits"); 846022Sgblack@eecs.umich.edu fetch_misses 856022Sgblack@eecs.umich.edu .name(name() + ".fetch_misses") 866022Sgblack@eecs.umich.edu .desc("ITB misses"); 876022Sgblack@eecs.umich.edu fetch_acv 886022Sgblack@eecs.umich.edu .name(name() + ".fetch_acv") 896022Sgblack@eecs.umich.edu .desc("ITB acv"); 906022Sgblack@eecs.umich.edu fetch_accesses 916022Sgblack@eecs.umich.edu .name(name() + ".fetch_accesses") 926022Sgblack@eecs.umich.edu .desc("ITB accesses"); 936022Sgblack@eecs.umich.edu 946022Sgblack@eecs.umich.edu fetch_accesses = fetch_hits + fetch_misses; 956022Sgblack@eecs.umich.edu 966022Sgblack@eecs.umich.edu read_hits 976022Sgblack@eecs.umich.edu .name(name() + ".read_hits") 986022Sgblack@eecs.umich.edu .desc("DTB read hits") 996022Sgblack@eecs.umich.edu ; 1006022Sgblack@eecs.umich.edu 1016022Sgblack@eecs.umich.edu read_misses 1026022Sgblack@eecs.umich.edu .name(name() + ".read_misses") 1036022Sgblack@eecs.umich.edu .desc("DTB read misses") 1046022Sgblack@eecs.umich.edu ; 1056022Sgblack@eecs.umich.edu 1066022Sgblack@eecs.umich.edu read_acv 1076022Sgblack@eecs.umich.edu .name(name() + ".read_acv") 1086022Sgblack@eecs.umich.edu .desc("DTB read access violations") 1096022Sgblack@eecs.umich.edu ; 1106022Sgblack@eecs.umich.edu 1116022Sgblack@eecs.umich.edu read_accesses 1126022Sgblack@eecs.umich.edu .name(name() + ".read_accesses") 1136022Sgblack@eecs.umich.edu .desc("DTB read accesses") 1146022Sgblack@eecs.umich.edu ; 1156022Sgblack@eecs.umich.edu 1166022Sgblack@eecs.umich.edu write_hits 1176022Sgblack@eecs.umich.edu .name(name() + ".write_hits") 1186022Sgblack@eecs.umich.edu .desc("DTB write hits") 1196022Sgblack@eecs.umich.edu ; 1206022Sgblack@eecs.umich.edu 1216022Sgblack@eecs.umich.edu write_misses 1226022Sgblack@eecs.umich.edu .name(name() + ".write_misses") 1236022Sgblack@eecs.umich.edu .desc("DTB write misses") 1246022Sgblack@eecs.umich.edu ; 1256022Sgblack@eecs.umich.edu 1266022Sgblack@eecs.umich.edu write_acv 1276022Sgblack@eecs.umich.edu .name(name() + ".write_acv") 1286022Sgblack@eecs.umich.edu .desc("DTB write access violations") 1296022Sgblack@eecs.umich.edu ; 1306022Sgblack@eecs.umich.edu 1316022Sgblack@eecs.umich.edu write_accesses 1326022Sgblack@eecs.umich.edu .name(name() + ".write_accesses") 1336022Sgblack@eecs.umich.edu .desc("DTB write accesses") 1346022Sgblack@eecs.umich.edu ; 1356022Sgblack@eecs.umich.edu 1366022Sgblack@eecs.umich.edu data_hits 1376022Sgblack@eecs.umich.edu .name(name() + ".data_hits") 1386022Sgblack@eecs.umich.edu .desc("DTB hits") 1396022Sgblack@eecs.umich.edu ; 1406022Sgblack@eecs.umich.edu 1416022Sgblack@eecs.umich.edu data_misses 1426022Sgblack@eecs.umich.edu .name(name() + ".data_misses") 1436022Sgblack@eecs.umich.edu .desc("DTB misses") 1446022Sgblack@eecs.umich.edu ; 1456022Sgblack@eecs.umich.edu 1466022Sgblack@eecs.umich.edu data_acv 1476022Sgblack@eecs.umich.edu .name(name() + ".data_acv") 1486022Sgblack@eecs.umich.edu .desc("DTB access violations") 1496022Sgblack@eecs.umich.edu ; 1506022Sgblack@eecs.umich.edu 1516022Sgblack@eecs.umich.edu data_accesses 1526022Sgblack@eecs.umich.edu .name(name() + ".data_accesses") 1536022Sgblack@eecs.umich.edu .desc("DTB accesses") 1546022Sgblack@eecs.umich.edu ; 1556022Sgblack@eecs.umich.edu 1566022Sgblack@eecs.umich.edu data_hits = read_hits + write_hits; 1576022Sgblack@eecs.umich.edu data_misses = read_misses + write_misses; 1586022Sgblack@eecs.umich.edu data_acv = read_acv + write_acv; 1596022Sgblack@eecs.umich.edu data_accesses = read_accesses + write_accesses; 1606022Sgblack@eecs.umich.edu} 1616022Sgblack@eecs.umich.edu 1623838Shsul@eecs.umich.edu// look up an entry in the TLB 1635004Sgblack@eecs.umich.eduTlbEntry * 1644967Sacolyte@umich.eduTLB::lookup(Addr vpn, uint8_t asn) 1653838Shsul@eecs.umich.edu{ 1663838Shsul@eecs.umich.edu // assume not found... 1675004Sgblack@eecs.umich.edu TlbEntry *retval = NULL; 1682SN/A 1695004Sgblack@eecs.umich.edu if (EntryCache[0]) { 1705004Sgblack@eecs.umich.edu if (vpn == EntryCache[0]->tag && 1715004Sgblack@eecs.umich.edu (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 1725004Sgblack@eecs.umich.edu retval = EntryCache[0]; 1735004Sgblack@eecs.umich.edu else if (EntryCache[1]) { 1745004Sgblack@eecs.umich.edu if (vpn == EntryCache[1]->tag && 1755004Sgblack@eecs.umich.edu (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 1765004Sgblack@eecs.umich.edu retval = EntryCache[1]; 1775004Sgblack@eecs.umich.edu else if (EntryCache[2] && vpn == EntryCache[2]->tag && 1785004Sgblack@eecs.umich.edu (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 1795004Sgblack@eecs.umich.edu retval = EntryCache[2]; 1804962Sacolyte@umich.edu } 1814962Sacolyte@umich.edu } 1824962Sacolyte@umich.edu 1834967Sacolyte@umich.edu if (retval == NULL) { 1844957Sacolyte@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 1854957Sacolyte@umich.edu if (i != lookupTable.end()) { 1864957Sacolyte@umich.edu while (i->first == vpn) { 1874957Sacolyte@umich.edu int index = i->second; 1885004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 1895004Sgblack@eecs.umich.edu assert(entry->valid); 1905004Sgblack@eecs.umich.edu if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1915004Sgblack@eecs.umich.edu retval = updateCache(entry); 1924957Sacolyte@umich.edu break; 1934957Sacolyte@umich.edu } 1944957Sacolyte@umich.edu 1954957Sacolyte@umich.edu ++i; 1961413SN/A } 1971413SN/A } 1982SN/A } 1992SN/A 2003838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 2013838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 2023838Shsul@eecs.umich.edu return retval; 2033838Shsul@eecs.umich.edu} 2042SN/A 2053838Shsul@eecs.umich.eduFault 20612749Sgiacomo.travaglini@arm.comTLB::checkCacheability(const RequestPtr &req, bool itb) 2073838Shsul@eecs.umich.edu{ 2085569Snate@binkert.org // in Alpha, cacheability is controlled by upper-level bits of the 2095569Snate@binkert.org // physical address 2103838Shsul@eecs.umich.edu 2115569Snate@binkert.org /* 2125569Snate@binkert.org * We support having the uncacheable bit in either bit 39 or bit 2135569Snate@binkert.org * 40. The Turbolaser platform (and EV5) support having the bit 2145569Snate@binkert.org * in 39, but Tsunami (which Linux assumes uses an EV6) generates 2155569Snate@binkert.org * accesses with the bit in 40. So we must check for both, but we 2165569Snate@binkert.org * have debug flags to catch a weird case where both are used, 2175569Snate@binkert.org * which shouldn't happen. 2185569Snate@binkert.org */ 2193838Shsul@eecs.umich.edu 2203838Shsul@eecs.umich.edu 2216025Snate@binkert.org if (req->getPaddr() & PAddrUncachedBit43) { 2223838Shsul@eecs.umich.edu // IPR memory space not implemented 2233838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 22410474Sandreas.hansson@arm.com return std::make_shared<UnimpFault>( 22510474Sandreas.hansson@arm.com "IPR memory space not implemented!"); 2263838Shsul@eecs.umich.edu } else { 2273838Shsul@eecs.umich.edu // mark request as uncacheable 22810824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 2293838Shsul@eecs.umich.edu 2305569Snate@binkert.org // Clear bits 42:35 of the physical address (10-2 in 2315569Snate@binkert.org // Tsunami manual) 2323838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 233924SN/A } 2345532Ssaidi@eecs.umich.edu // We shouldn't be able to read from an uncachable address in Alpha as 23511320Ssteve.reinhardt@amd.com // we don't have a ROM and we don't want to try to fetch from a device 23611320Ssteve.reinhardt@amd.com // register as we destroy any data that is clear-on-read. 23711320Ssteve.reinhardt@amd.com if (req->isUncacheable() && itb) 23810474Sandreas.hansson@arm.com return std::make_shared<UnimpFault>( 23910474Sandreas.hansson@arm.com "CPU trying to fetch from uncached I/O"); 2405532Ssaidi@eecs.umich.edu 2412SN/A } 2423838Shsul@eecs.umich.edu return NoFault; 2433838Shsul@eecs.umich.edu} 2442SN/A 2452SN/A 2463838Shsul@eecs.umich.edu// insert a new TLB entry 2473838Shsul@eecs.umich.eduvoid 2485004Sgblack@eecs.umich.eduTLB::insert(Addr addr, TlbEntry &entry) 2493838Shsul@eecs.umich.edu{ 2504957Sacolyte@umich.edu flushCache(); 2513838Shsul@eecs.umich.edu VAddr vaddr = addr; 2523838Shsul@eecs.umich.edu if (table[nlu].valid) { 2533838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 2543838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 2553838Shsul@eecs.umich.edu 2563838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2573838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2583838Shsul@eecs.umich.edu 2593838Shsul@eecs.umich.edu int index; 2603838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 2613838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 2623838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2633838Shsul@eecs.umich.edu 2643838Shsul@eecs.umich.edu ++i; 2653838Shsul@eecs.umich.edu } 2663838Shsul@eecs.umich.edu 2673838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 2683838Shsul@eecs.umich.edu 2693838Shsul@eecs.umich.edu lookupTable.erase(i); 2703838Shsul@eecs.umich.edu } 2713838Shsul@eecs.umich.edu 2725004Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 2733838Shsul@eecs.umich.edu 2745004Sgblack@eecs.umich.edu table[nlu] = entry; 2753838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 2763838Shsul@eecs.umich.edu table[nlu].valid = true; 2773838Shsul@eecs.umich.edu 2783838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 2793838Shsul@eecs.umich.edu nextnlu(); 2803838Shsul@eecs.umich.edu} 2813838Shsul@eecs.umich.edu 2823838Shsul@eecs.umich.eduvoid 2833838Shsul@eecs.umich.eduTLB::flushAll() 2843838Shsul@eecs.umich.edu{ 2853838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 28610905Sandreas.sandberg@arm.com std::fill(table.begin(), table.end(), TlbEntry()); 2874957Sacolyte@umich.edu flushCache(); 2883838Shsul@eecs.umich.edu lookupTable.clear(); 2893838Shsul@eecs.umich.edu nlu = 0; 2903838Shsul@eecs.umich.edu} 2913838Shsul@eecs.umich.edu 2923838Shsul@eecs.umich.eduvoid 2933838Shsul@eecs.umich.eduTLB::flushProcesses() 2943838Shsul@eecs.umich.edu{ 2954957Sacolyte@umich.edu flushCache(); 2963838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 2973838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 2983838Shsul@eecs.umich.edu while (i != end) { 2993838Shsul@eecs.umich.edu int index = i->second; 3005004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 3015004Sgblack@eecs.umich.edu assert(entry->valid); 3023838Shsul@eecs.umich.edu 3033838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 3043838Shsul@eecs.umich.edu // increment it to get the next entry now 3053838Shsul@eecs.umich.edu PageTable::iterator cur = i; 3063838Shsul@eecs.umich.edu ++i; 3073838Shsul@eecs.umich.edu 3085004Sgblack@eecs.umich.edu if (!entry->asma) { 3095569Snate@binkert.org DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, 3105569Snate@binkert.org entry->tag, entry->ppn); 3115004Sgblack@eecs.umich.edu entry->valid = false; 3123838Shsul@eecs.umich.edu lookupTable.erase(cur); 3133453Sgblack@eecs.umich.edu } 3143453Sgblack@eecs.umich.edu } 3153838Shsul@eecs.umich.edu} 3162SN/A 3173838Shsul@eecs.umich.eduvoid 3183838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 3193838Shsul@eecs.umich.edu{ 3204957Sacolyte@umich.edu flushCache(); 3213838Shsul@eecs.umich.edu VAddr vaddr = addr; 3222SN/A 3233838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 3243838Shsul@eecs.umich.edu if (i == lookupTable.end()) 3253838Shsul@eecs.umich.edu return; 3262SN/A 3274428Ssaidi@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 3283838Shsul@eecs.umich.edu int index = i->second; 3295004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 3305004Sgblack@eecs.umich.edu assert(entry->valid); 3313453Sgblack@eecs.umich.edu 3325004Sgblack@eecs.umich.edu if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 3333838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 3345004Sgblack@eecs.umich.edu entry->ppn); 3353453Sgblack@eecs.umich.edu 3363838Shsul@eecs.umich.edu // invalidate this entry 3375004Sgblack@eecs.umich.edu entry->valid = false; 3383838Shsul@eecs.umich.edu 3394428Ssaidi@eecs.umich.edu lookupTable.erase(i++); 3404428Ssaidi@eecs.umich.edu } else { 3414428Ssaidi@eecs.umich.edu ++i; 3423838Shsul@eecs.umich.edu } 3433838Shsul@eecs.umich.edu } 3443838Shsul@eecs.umich.edu} 3453838Shsul@eecs.umich.edu 3463838Shsul@eecs.umich.edu 3473838Shsul@eecs.umich.eduvoid 34810905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 3493838Shsul@eecs.umich.edu{ 35010905Sandreas.sandberg@arm.com const unsigned size(table.size()); 3513838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 3523838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 3533838Shsul@eecs.umich.edu 35410905Sandreas.sandberg@arm.com for (int i = 0; i < size; i++) 35510905Sandreas.sandberg@arm.com table[i].serializeSection(cp, csprintf("Entry%d", i)); 3563838Shsul@eecs.umich.edu} 3573838Shsul@eecs.umich.edu 3583838Shsul@eecs.umich.eduvoid 35910905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 3603838Shsul@eecs.umich.edu{ 36110905Sandreas.sandberg@arm.com unsigned size(0); 3623838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 3633838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 3643838Shsul@eecs.umich.edu 36510905Sandreas.sandberg@arm.com table.resize(size); 3663838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 36710905Sandreas.sandberg@arm.com table[i].unserializeSection(cp, csprintf("Entry%d", i)); 3683838Shsul@eecs.umich.edu if (table[i].valid) { 3693838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 3703838Shsul@eecs.umich.edu } 3713838Shsul@eecs.umich.edu } 3723838Shsul@eecs.umich.edu} 3733838Shsul@eecs.umich.edu 3743838Shsul@eecs.umich.eduFault 37512749Sgiacomo.travaglini@arm.comTLB::translateInst(const RequestPtr &req, ThreadContext *tc) 3763838Shsul@eecs.umich.edu{ 3774375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 3788738Sgblack@eecs.umich.edu if (FullSystem && PcPAL(req->getPC())) 3795736Snate@binkert.org req->setFlags(Request::PHYSICAL); 3804375Sgblack@eecs.umich.edu 3813838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3823838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3833838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3846022Sgblack@eecs.umich.edu fetch_hits++; 3853838Shsul@eecs.umich.edu return NoFault; 3863453Sgblack@eecs.umich.edu } 3873453Sgblack@eecs.umich.edu 3885736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 3893838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3903838Shsul@eecs.umich.edu } else { 3913838Shsul@eecs.umich.edu // verify that this is a good virtual address 3923838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3936022Sgblack@eecs.umich.edu fetch_acv++; 39410474Sandreas.hansson@arm.com return std::make_shared<ItbAcvFault>(req->getVaddr()); 3952SN/A } 3962SN/A 3973838Shsul@eecs.umich.edu 3983838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3993838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 4006025Snate@binkert.org if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 4013838Shsul@eecs.umich.edu // only valid in kernel mode 4024172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 4033838Shsul@eecs.umich.edu mode_kernel) { 4046022Sgblack@eecs.umich.edu fetch_acv++; 40510474Sandreas.hansson@arm.com return std::make_shared<ItbAcvFault>(req->getVaddr()); 406555SN/A } 4072SN/A 4083838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 409551SN/A 4103838Shsul@eecs.umich.edu // sign extend the physical address properly 4113838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 4123838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 4133838Shsul@eecs.umich.edu else 4143838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 4153838Shsul@eecs.umich.edu } else { 4163838Shsul@eecs.umich.edu // not a physical address: need to look up pte 4174172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 4185004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 4193838Shsul@eecs.umich.edu asn); 4203838Shsul@eecs.umich.edu 4215004Sgblack@eecs.umich.edu if (!entry) { 4226022Sgblack@eecs.umich.edu fetch_misses++; 42310474Sandreas.hansson@arm.com return std::make_shared<ItbPageFault>(req->getVaddr()); 4243838Shsul@eecs.umich.edu } 4253838Shsul@eecs.umich.edu 4265004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 4273838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 4283838Shsul@eecs.umich.edu & ~3)); 4293838Shsul@eecs.umich.edu 4303838Shsul@eecs.umich.edu // check permissions for this access 4315004Sgblack@eecs.umich.edu if (!(entry->xre & 4324172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 4333838Shsul@eecs.umich.edu // instruction access fault 4346022Sgblack@eecs.umich.edu fetch_acv++; 43510474Sandreas.hansson@arm.com return std::make_shared<ItbAcvFault>(req->getVaddr()); 4363838Shsul@eecs.umich.edu } 4373838Shsul@eecs.umich.edu 4386022Sgblack@eecs.umich.edu fetch_hits++; 4393838Shsul@eecs.umich.edu } 4403838Shsul@eecs.umich.edu } 4413838Shsul@eecs.umich.edu 4423838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 4438591Sgblack@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) { 44410474Sandreas.hansson@arm.com return std::make_shared<MachineCheckFault>(); 4458591Sgblack@eecs.umich.edu } 4463838Shsul@eecs.umich.edu 4475532Ssaidi@eecs.umich.edu return checkCacheability(req, true); 4483838Shsul@eecs.umich.edu 4493838Shsul@eecs.umich.edu} 4503838Shsul@eecs.umich.edu 4513838Shsul@eecs.umich.eduFault 45212749Sgiacomo.travaglini@arm.comTLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) 4533838Shsul@eecs.umich.edu{ 4543838Shsul@eecs.umich.edu mode_type mode = 4554172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4563838Shsul@eecs.umich.edu 4573838Shsul@eecs.umich.edu /** 4583838Shsul@eecs.umich.edu * Check for alignment faults 4593838Shsul@eecs.umich.edu */ 4603838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4616185Sksewell@umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), 4623838Shsul@eecs.umich.edu req->getSize()); 4633838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 46410474Sandreas.hansson@arm.com return std::make_shared<DtbAlignmentFault>(req->getVaddr(), 46510474Sandreas.hansson@arm.com req->getFlags(), 46610474Sandreas.hansson@arm.com flags); 4673838Shsul@eecs.umich.edu } 4683838Shsul@eecs.umich.edu 4698408Sksewell@umich.edu if (PcPAL(req->getPC())) { 47010823SAndreas.Sandberg@ARM.com mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ? 4713838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 4724172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 4733838Shsul@eecs.umich.edu : mode_kernel; 4743838Shsul@eecs.umich.edu } 4753838Shsul@eecs.umich.edu 4765736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 4773838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 4783838Shsul@eecs.umich.edu } else { 4793838Shsul@eecs.umich.edu // verify that this is a good virtual address 4803838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 4813838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4823838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 4833838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 4843838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 48510474Sandreas.hansson@arm.com return std::make_shared<DtbPageFault>(req->getVaddr(), 48610474Sandreas.hansson@arm.com req->getFlags(), 48710474Sandreas.hansson@arm.com flags); 4883838Shsul@eecs.umich.edu } 4893838Shsul@eecs.umich.edu 4903838Shsul@eecs.umich.edu // Check for "superpage" mapping 4916025Snate@binkert.org if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 4923838Shsul@eecs.umich.edu // only valid in kernel mode 4934172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 4943838Shsul@eecs.umich.edu mode_kernel) { 4953838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4963838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 4973838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 4985569Snate@binkert.org 49910474Sandreas.hansson@arm.com return std::make_shared<DtbAcvFault>(req->getVaddr(), 50010474Sandreas.hansson@arm.com req->getFlags(), 50110474Sandreas.hansson@arm.com flags); 5023838Shsul@eecs.umich.edu } 5033838Shsul@eecs.umich.edu 5043838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5053838Shsul@eecs.umich.edu 5063838Shsul@eecs.umich.edu // sign extend the physical address properly 5073838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 5083838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 5093838Shsul@eecs.umich.edu else 5103838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 5113838Shsul@eecs.umich.edu } else { 5123838Shsul@eecs.umich.edu if (write) 5133838Shsul@eecs.umich.edu write_accesses++; 5143838Shsul@eecs.umich.edu else 5153838Shsul@eecs.umich.edu read_accesses++; 5163838Shsul@eecs.umich.edu 5174172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5183838Shsul@eecs.umich.edu 5193838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5205004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 5213838Shsul@eecs.umich.edu 5225004Sgblack@eecs.umich.edu if (!entry) { 5233838Shsul@eecs.umich.edu // page fault 5243838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5253838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5263838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 52710823SAndreas.Sandberg@ARM.com return (req->getFlags() & AlphaRequestFlags::VPTE) ? 52810474Sandreas.hansson@arm.com (Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(), 52910474Sandreas.hansson@arm.com req->getFlags(), 53010474Sandreas.hansson@arm.com flags)) : 53110474Sandreas.hansson@arm.com (Fault)(std::make_shared<NDtbMissFault>(req->getVaddr(), 53210474Sandreas.hansson@arm.com req->getFlags(), 53310474Sandreas.hansson@arm.com flags)); 5343838Shsul@eecs.umich.edu } 5353838Shsul@eecs.umich.edu 5365004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 5373838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5383838Shsul@eecs.umich.edu 5393838Shsul@eecs.umich.edu if (write) { 5405004Sgblack@eecs.umich.edu if (!(entry->xwe & MODE2MASK(mode))) { 5413838Shsul@eecs.umich.edu // declare the instruction access fault 5423838Shsul@eecs.umich.edu write_acv++; 5433838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5443838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5455004Sgblack@eecs.umich.edu (entry->fonw ? MM_STAT_FONW_MASK : 0); 54610474Sandreas.hansson@arm.com return std::make_shared<DtbPageFault>(req->getVaddr(), 54710474Sandreas.hansson@arm.com req->getFlags(), 54810474Sandreas.hansson@arm.com flags); 5493838Shsul@eecs.umich.edu } 5505004Sgblack@eecs.umich.edu if (entry->fonw) { 5513838Shsul@eecs.umich.edu write_acv++; 5525569Snate@binkert.org uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; 55310474Sandreas.hansson@arm.com return std::make_shared<DtbPageFault>(req->getVaddr(), 55410474Sandreas.hansson@arm.com req->getFlags(), 55510474Sandreas.hansson@arm.com flags); 5563838Shsul@eecs.umich.edu } 5573453Sgblack@eecs.umich.edu } else { 5585004Sgblack@eecs.umich.edu if (!(entry->xre & MODE2MASK(mode))) { 5593838Shsul@eecs.umich.edu read_acv++; 5603838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5615004Sgblack@eecs.umich.edu (entry->fonr ? MM_STAT_FONR_MASK : 0); 56210474Sandreas.hansson@arm.com return std::make_shared<DtbAcvFault>(req->getVaddr(), 56310474Sandreas.hansson@arm.com req->getFlags(), 56410474Sandreas.hansson@arm.com flags); 5653453Sgblack@eecs.umich.edu } 5665004Sgblack@eecs.umich.edu if (entry->fonr) { 5673838Shsul@eecs.umich.edu read_acv++; 5683838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 56910474Sandreas.hansson@arm.com return std::make_shared<DtbPageFault>(req->getVaddr(), 57010474Sandreas.hansson@arm.com req->getFlags(), 57110474Sandreas.hansson@arm.com flags); 5723453Sgblack@eecs.umich.edu } 5732SN/A } 5742SN/A } 575551SN/A 5763838Shsul@eecs.umich.edu if (write) 5773838Shsul@eecs.umich.edu write_hits++; 5783838Shsul@eecs.umich.edu else 5793838Shsul@eecs.umich.edu read_hits++; 5802SN/A } 5812SN/A 5823838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 5838591Sgblack@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) { 58410474Sandreas.hansson@arm.com return std::make_shared<MachineCheckFault>(); 5858591Sgblack@eecs.umich.edu } 586551SN/A 5873838Shsul@eecs.umich.edu return checkCacheability(req); 5883838Shsul@eecs.umich.edu} 5893453Sgblack@eecs.umich.edu 5905004Sgblack@eecs.umich.eduTlbEntry & 5913838Shsul@eecs.umich.eduTLB::index(bool advance) 5923838Shsul@eecs.umich.edu{ 5935004Sgblack@eecs.umich.edu TlbEntry *entry = &table[nlu]; 5943453Sgblack@eecs.umich.edu 5953838Shsul@eecs.umich.edu if (advance) 5963838Shsul@eecs.umich.edu nextnlu(); 5973453Sgblack@eecs.umich.edu 5985004Sgblack@eecs.umich.edu return *entry; 5993838Shsul@eecs.umich.edu} 6003453Sgblack@eecs.umich.edu 6016022Sgblack@eecs.umich.eduFault 60212749Sgiacomo.travaglini@arm.comTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 6036022Sgblack@eecs.umich.edu{ 6046023Snate@binkert.org if (mode == Execute) 6056022Sgblack@eecs.umich.edu return translateInst(req, tc); 6066022Sgblack@eecs.umich.edu else 6076023Snate@binkert.org return translateData(req, tc, mode == Write); 6086022Sgblack@eecs.umich.edu} 6096022Sgblack@eecs.umich.edu 6106022Sgblack@eecs.umich.eduvoid 61112749Sgiacomo.travaglini@arm.comTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, 6126023Snate@binkert.org Translation *translation, Mode mode) 6136022Sgblack@eecs.umich.edu{ 6146022Sgblack@eecs.umich.edu assert(translation); 6156023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 6166022Sgblack@eecs.umich.edu} 6176022Sgblack@eecs.umich.edu 6188888Sgeoffrey.blake@arm.comFault 61912749Sgiacomo.travaglini@arm.comTLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc, 62012749Sgiacomo.travaglini@arm.com Mode mode) const 6219738Sandreas@sandberg.pp.se{ 6229738Sandreas@sandberg.pp.se return NoFault; 6239738Sandreas@sandberg.pp.se} 6249738Sandreas@sandberg.pp.se 6257811Ssteve.reinhardt@amd.com} // namespace AlphaISA 6264088Sbinkertn@umich.edu 6276022Sgblack@eecs.umich.eduAlphaISA::TLB * 6286022Sgblack@eecs.umich.eduAlphaTLBParams::create() 6293838Shsul@eecs.umich.edu{ 6306022Sgblack@eecs.umich.edu return new AlphaISA::TLB(this); 6313838Shsul@eecs.umich.edu} 632