16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2001-2005 The Regents of The University of Michigan 36691Stjones1@inf.ed.ac.uk * Copyright (c) 2007 MIPS Technologies, Inc. 46691Stjones1@inf.ed.ac.uk * Copyright (c) 2007-2008 The Florida State University 56691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 66691Stjones1@inf.ed.ac.uk * All rights reserved. 76691Stjones1@inf.ed.ac.uk * 86691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 96691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 106691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 116691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 126691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 136691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 146691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 156691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 166691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 176691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 186691Stjones1@inf.ed.ac.uk * 196691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 206691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 216691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 226691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 236691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 246691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 256691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 266691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 276691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 286691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 296691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 306691Stjones1@inf.ed.ac.uk * 316691Stjones1@inf.ed.ac.uk * Authors: Nathan Binkert 326691Stjones1@inf.ed.ac.uk * Steve Reinhardt 336691Stjones1@inf.ed.ac.uk * Stephen Hines 346691Stjones1@inf.ed.ac.uk * Timothy M. Jones 356691Stjones1@inf.ed.ac.uk */ 366691Stjones1@inf.ed.ac.uk 376691Stjones1@inf.ed.ac.uk#ifndef __ARCH_POWER_TLB_HH__ 386691Stjones1@inf.ed.ac.uk#define __ARCH_POWER_TLB_HH__ 396691Stjones1@inf.ed.ac.uk 406691Stjones1@inf.ed.ac.uk#include <map> 416691Stjones1@inf.ed.ac.uk 4210687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 436691Stjones1@inf.ed.ac.uk#include "arch/power/isa_traits.hh" 448229Snate@binkert.org#include "arch/power/pagetable.hh" 456691Stjones1@inf.ed.ac.uk#include "arch/power/utility.hh" 466691Stjones1@inf.ed.ac.uk#include "arch/power/vtophys.hh" 476691Stjones1@inf.ed.ac.uk#include "base/statistics.hh" 486691Stjones1@inf.ed.ac.uk#include "mem/request.hh" 496691Stjones1@inf.ed.ac.uk#include "params/PowerTLB.hh" 506691Stjones1@inf.ed.ac.uk 516691Stjones1@inf.ed.ac.ukclass ThreadContext; 526691Stjones1@inf.ed.ac.uk 536691Stjones1@inf.ed.ac.uknamespace PowerISA { 546691Stjones1@inf.ed.ac.uk 556691Stjones1@inf.ed.ac.uk// This is copied from the ARM ISA and has not been checked against the 566691Stjones1@inf.ed.ac.uk// Power at all. 576691Stjones1@inf.ed.ac.ukstruct TlbEntry 586691Stjones1@inf.ed.ac.uk{ 596691Stjones1@inf.ed.ac.uk Addr _pageStart; 606691Stjones1@inf.ed.ac.uk 616691Stjones1@inf.ed.ac.uk TlbEntry() 626691Stjones1@inf.ed.ac.uk { 636691Stjones1@inf.ed.ac.uk } 646691Stjones1@inf.ed.ac.uk 6510558Salexandru.dutu@amd.com TlbEntry(Addr asn, Addr vaddr, Addr paddr, 6610558Salexandru.dutu@amd.com bool uncacheable, bool read_only) 676691Stjones1@inf.ed.ac.uk : _pageStart(paddr) 686691Stjones1@inf.ed.ac.uk { 6910558Salexandru.dutu@amd.com if (uncacheable || read_only) 7010558Salexandru.dutu@amd.com warn("Power TlbEntry does not support uncacheable" 7110558Salexandru.dutu@amd.com " or read-only mappings\n"); 726691Stjones1@inf.ed.ac.uk } 736691Stjones1@inf.ed.ac.uk 746691Stjones1@inf.ed.ac.uk void 756691Stjones1@inf.ed.ac.uk updateVaddr(Addr new_vaddr) 766691Stjones1@inf.ed.ac.uk { 776691Stjones1@inf.ed.ac.uk panic("unimplemented"); 786691Stjones1@inf.ed.ac.uk } 796691Stjones1@inf.ed.ac.uk 806691Stjones1@inf.ed.ac.uk Addr 816691Stjones1@inf.ed.ac.uk pageStart() 826691Stjones1@inf.ed.ac.uk { 836691Stjones1@inf.ed.ac.uk return _pageStart; 846691Stjones1@inf.ed.ac.uk } 856691Stjones1@inf.ed.ac.uk 866691Stjones1@inf.ed.ac.uk void 8710905Sandreas.sandberg@arm.com serialize(CheckpointOut &cp) const 886691Stjones1@inf.ed.ac.uk { 896691Stjones1@inf.ed.ac.uk SERIALIZE_SCALAR(_pageStart); 906691Stjones1@inf.ed.ac.uk } 916691Stjones1@inf.ed.ac.uk 926691Stjones1@inf.ed.ac.uk void 9310905Sandreas.sandberg@arm.com unserialize(CheckpointIn &cp) 946691Stjones1@inf.ed.ac.uk { 956691Stjones1@inf.ed.ac.uk UNSERIALIZE_SCALAR(_pageStart); 966691Stjones1@inf.ed.ac.uk } 976691Stjones1@inf.ed.ac.uk}; 986691Stjones1@inf.ed.ac.uk 996691Stjones1@inf.ed.ac.ukclass TLB : public BaseTLB 1006691Stjones1@inf.ed.ac.uk{ 1016691Stjones1@inf.ed.ac.uk protected: 1026691Stjones1@inf.ed.ac.uk typedef std::multimap<Addr, int> PageTable; 1036691Stjones1@inf.ed.ac.uk PageTable lookupTable; // Quick lookup into page table 1046691Stjones1@inf.ed.ac.uk 1056691Stjones1@inf.ed.ac.uk PowerISA::PTE *table; // the Page Table 1066691Stjones1@inf.ed.ac.uk int size; // TLB Size 1076691Stjones1@inf.ed.ac.uk int nlu; // not last used entry (for replacement) 1086691Stjones1@inf.ed.ac.uk 1096691Stjones1@inf.ed.ac.uk void 1106691Stjones1@inf.ed.ac.uk nextnlu() 1116691Stjones1@inf.ed.ac.uk { 1126691Stjones1@inf.ed.ac.uk if (++nlu >= size) { 1136691Stjones1@inf.ed.ac.uk nlu = 0; 1146691Stjones1@inf.ed.ac.uk } 1156691Stjones1@inf.ed.ac.uk } 1166691Stjones1@inf.ed.ac.uk 1176691Stjones1@inf.ed.ac.uk PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const; 1186691Stjones1@inf.ed.ac.uk 1196691Stjones1@inf.ed.ac.uk mutable Stats::Scalar read_hits; 1206691Stjones1@inf.ed.ac.uk mutable Stats::Scalar read_misses; 1216691Stjones1@inf.ed.ac.uk mutable Stats::Scalar read_acv; 1226691Stjones1@inf.ed.ac.uk mutable Stats::Scalar read_accesses; 1236691Stjones1@inf.ed.ac.uk mutable Stats::Scalar write_hits; 1246691Stjones1@inf.ed.ac.uk mutable Stats::Scalar write_misses; 1256691Stjones1@inf.ed.ac.uk mutable Stats::Scalar write_acv; 1266691Stjones1@inf.ed.ac.uk mutable Stats::Scalar write_accesses; 1276691Stjones1@inf.ed.ac.uk Stats::Formula hits; 1286691Stjones1@inf.ed.ac.uk Stats::Formula misses; 1296691Stjones1@inf.ed.ac.uk Stats::Formula accesses; 1306691Stjones1@inf.ed.ac.uk 1316691Stjones1@inf.ed.ac.uk public: 1326691Stjones1@inf.ed.ac.uk typedef PowerTLBParams Params; 1336691Stjones1@inf.ed.ac.uk TLB(const Params *p); 1346691Stjones1@inf.ed.ac.uk virtual ~TLB(); 1356691Stjones1@inf.ed.ac.uk 13611347Sandreas.hansson@arm.com void takeOverFrom(BaseTLB *otlb) override {} 13710194SGeoffrey.Blake@arm.com 1386691Stjones1@inf.ed.ac.uk int probeEntry(Addr vpn,uint8_t) const; 1396691Stjones1@inf.ed.ac.uk PowerISA::PTE *getEntry(unsigned) const; 1406691Stjones1@inf.ed.ac.uk 1416691Stjones1@inf.ed.ac.uk int smallPages; 1426691Stjones1@inf.ed.ac.uk 1436691Stjones1@inf.ed.ac.uk int 1446691Stjones1@inf.ed.ac.uk getsize() const 1456691Stjones1@inf.ed.ac.uk { 1466691Stjones1@inf.ed.ac.uk return size; 1476691Stjones1@inf.ed.ac.uk } 1486691Stjones1@inf.ed.ac.uk 1496691Stjones1@inf.ed.ac.uk PowerISA::PTE &index(bool advance = true); 1506691Stjones1@inf.ed.ac.uk void insert(Addr vaddr, PowerISA::PTE &pte); 1516691Stjones1@inf.ed.ac.uk void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages); 15211347Sandreas.hansson@arm.com void flushAll() override; 1536691Stjones1@inf.ed.ac.uk 1546691Stjones1@inf.ed.ac.uk void 15511347Sandreas.hansson@arm.com demapPage(Addr vaddr, uint64_t asn) override 1566691Stjones1@inf.ed.ac.uk { 1576691Stjones1@inf.ed.ac.uk panic("demapPage unimplemented.\n"); 1586691Stjones1@inf.ed.ac.uk } 1596691Stjones1@inf.ed.ac.uk 1606691Stjones1@inf.ed.ac.uk // static helper functions... really 1616691Stjones1@inf.ed.ac.uk static bool validVirtualAddress(Addr vaddr); 16212749Sgiacomo.travaglini@arm.com static Fault checkCacheability(const RequestPtr &req); 16312749Sgiacomo.travaglini@arm.com Fault translateInst(const RequestPtr &req, ThreadContext *tc); 16412749Sgiacomo.travaglini@arm.com Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write); 16512406Sgabeblack@google.com Fault translateAtomic( 16612749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, Mode mode) override; 16712406Sgabeblack@google.com void translateTiming( 16812749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, 16912406Sgabeblack@google.com Translation *translation, Mode mode) override; 17012406Sgabeblack@google.com Fault finalizePhysical( 17112749Sgiacomo.travaglini@arm.com const RequestPtr &req, 17212749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const override; 1736691Stjones1@inf.ed.ac.uk 1746691Stjones1@inf.ed.ac.uk // Checkpointing 17511168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 17611168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 17710905Sandreas.sandberg@arm.com 17811347Sandreas.hansson@arm.com void regStats() override; 1796691Stjones1@inf.ed.ac.uk}; 1806691Stjones1@inf.ed.ac.uk 1817811Ssteve.reinhardt@amd.com} // namespace PowerISA 1826691Stjones1@inf.ed.ac.uk 1836691Stjones1@inf.ed.ac.uk#endif // __ARCH_POWER_TLB_HH__ 184