/gem5/src/cpu/o3/ |
H A D | decode_impl.hh | 49 #include "cpu/o3/decode.hh" 50 #include "cpu/inst_seq.hh" 63 : cpu(_cpu), 73 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 120 return cpu->name() + ".decode"; 353 cpu->removeInstsUntil(squash_seq_num, tid); 469 cpu->activateStage(O3CPU::DecodeIdx); 478 cpu->deactivateStage(O3CPU::DecodeIdx); 596 cpu->activityThisCycle();
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H A D | decode.hh | 49 #include "cpu/timebuf.hh" 212 O3CPU *cpu; member in class:DefaultDecode
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H A D | rob.hh | 88 * @param _cpu The cpu object pointer. 89 * @param params The cpu params including several ROB-specific parameters. 271 O3CPU *cpu; member in class:ROB 308 * This will always be set to cpu->instList.end() if it is invalid.
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H A D | rename_impl.hh | 53 #include "cpu/o3/rename.hh" 54 #include "cpu/reg_class.hh" 64 : cpu(_cpu), 74 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 97 return cpu->name() + ".rename"; 209 ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 210 ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 461 cpu->activityThisCycle(); 894 cpu->activateStage(O3CPU::RenameIdx); 903 cpu [all...] |
H A D | inst_queue_impl.hh | 52 #include "cpu/o3/fu_pool.hh" 53 #include "cpu/o3/inst_queue.hh" 90 : cpu(cpu_ptr), 175 return cpu->name() + ".iq"; 302 issueRate = iqInstsIssued / cpu->numCycles; 755 assert(!cpu->switchedOut()); 875 cpu->schedule(execution, 876 cpu->clockEdge(Cycles(op_latency - 1))); 936 cpu->activityThisCycle(); 1166 cpu [all...] |
H A D | lsq.hh | 51 #include "cpu/inst_seq.hh" 52 #include "cpu/o3/lsq_unit.hh" 53 #include "cpu/utils.hh" 130 FullO3CPU<Impl> *cpu; member in class:LSQ::DcachePort 136 cpu(_cpu) 1040 O3CPU *cpu; member in class:LSQ::LSQRequest 1123 ThreadID tid = cpu->contextToThread(req->request()->contextId()); 1132 ThreadID tid = cpu->contextToThread(req->request()->contextId());
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H A D | rob_impl.hh | 50 #include "cpu/o3/rob.hh" 60 cpu(_cpu), 124 return cpu->name() + ".rob"; 273 cpu->removeFrontInst(head_inst);
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/gem5/src/gpu-compute/ |
H A D | shader.cc | 132 Shader::hostWakeUp(BaseCPU *cpu) { argument 133 if (cpuPointer == cpu) { 135 cpu->activateContext(gpuTc->threadId());
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H A D | shader.hh | 45 #include "cpu/simple/atomic.hh" 46 #include "cpu/simple/timing.hh" 47 #include "cpu/simple_thread.hh" 48 #include "cpu/thread_context.hh" 49 #include "cpu/thread_state.hh" 198 void hostWakeUp(BaseCPU *cpu);
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/gem5/src/arch/alpha/ |
H A D | ev5.cc | 39 #include "cpu/base.hh" 40 #include "cpu/simple_thread.hh" 41 #include "cpu/thread_context.hh" 85 zeroRegisters(CPU *cpu) argument 89 // cpu model. Consider changing later.) 90 cpu->thread->setIntReg(ZeroReg, 0); 91 cpu->thread->setFloatReg(ZeroReg, 0);
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/gem5/configs/ruby/ |
H A D | MOESI_hammer.py | 80 # First create the Ruby objects associated with this cpu 94 # number of cpu ports connected to the tester object, which 95 # is stored in system.cpu. because there is only ever one 97 # size of system.cpu; therefore if len(system.cpu) == 1 98 # we use system.cpu[0] to set the clk_domain, thereby ensuring 99 # we don't index off the end of the cpu list. 100 if len(system.cpu) == 1: 101 clk_domain = system.cpu[0].clk_domain 103 clk_domain = system.cpu[ [all...] |
H A D | MOESI_CMP_token.py | 85 # First create the Ruby objects associated with this cpu 95 # number of cpu ports connected to the tester object, which 96 # is stored in system.cpu. because there is only ever one 98 # size of system.cpu; therefore if len(system.cpu) == 1 99 # we use system.cpu[0] to set the clk_domain, thereby ensuring 100 # we don't index off the end of the cpu list. 101 if len(system.cpu) == 1: 102 clk_domain = system.cpu[0].clk_domain 104 clk_domain = system.cpu[ [all...] |
H A D | MESI_Three_Level.py | 90 # First create the Ruby objects associated with this cpu 101 # number of cpu ports connected to the tester object, which 102 # is stored in system.cpu. because there is only ever one 104 # size of system.cpu; therefore if len(system.cpu) == 1 105 # we use system.cpu[0] to set the clk_domain, thereby ensuring 106 # we don't index off the end of the cpu list. 107 if len(system.cpu) == 1: 108 clk_domain = system.cpu[0].clk_domain 110 clk_domain = system.cpu[ [all...] |
/gem5/configs/example/arm/ |
H A D | fs_bigLITTLE.py | 176 parser.add_argument("--cpu-type", type=str, choices=cpu_types.keys(), 189 parser.add_argument("--big-cpu-clock", type=str, default="2GHz", 191 parser.add_argument("--little-cpu-clock", type=str, default="1GHz", 200 "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' " 289 for idx, cpu in enumerate(cpus): 293 for obj in cpu.descendants(): 295 cpu.eventq_index = first_cpu_eq + idx
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/gem5/src/cpu/minor/ |
H A D | lsq.hh | 50 #include "cpu/minor/buffers.hh" 51 #include "cpu/minor/cpu.hh" 52 #include "cpu/minor/pipe_data.hh" 53 #include "cpu/minor/trace.hh" 65 MinorCPU &cpu; member in class:Minor::LSQ 96 DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu) : argument 97 MinorCPU::MinorCPUPort(name, cpu), lsq(lsq_)
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H A D | fetch2.hh | 50 #include "cpu/minor/buffers.hh" 51 #include "cpu/minor/cpu.hh" 52 #include "cpu/minor/pipe_data.hh" 53 #include "cpu/pred/bpred_unit.hh" 65 MinorCPU &cpu; member in class:Minor::Fetch2
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H A D | exec_context.hh | 56 #include "cpu/exec_context.hh" 57 #include "cpu/minor/execute.hh" 58 #include "cpu/minor/pipeline.hh" 59 #include "cpu/base.hh" 60 #include "cpu/simple_thread.hh" 77 MinorCPU &cpu; member in class:Minor::ExecContext 92 cpu(cpu_), 443 BaseCPU *getCpuPtr() { return &cpu; }
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H A D | execute.hh | 50 #include "cpu/minor/buffers.hh" 51 #include "cpu/minor/cpu.hh" 52 #include "cpu/minor/func_unit.hh" 53 #include "cpu/minor/lsq.hh" 54 #include "cpu/minor/pipe_data.hh" 55 #include "cpu/minor/scoreboard.hh" 72 MinorCPU &cpu; member in class:Minor::Execute
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/gem5/src/dev/sparc/ |
H A D | iob.hh | 92 int cpu; member in struct:Iob::IntMan
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/gem5/configs/example/ |
H A D | ruby_random_test.py | 104 system = System(cpu = tester, mem_ranges = [AddrRange(options.mem_size)]) 130 # Tie the ruby tester ports to the ruby cpu read and write ports
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/gem5/tests/configs/ |
H A D | gpu-randomtest-ruby.py | 92 # We set the testers as cpu for ruby to find the correct clock domains 94 system = System(cpu = tester) 119 # Tie the ruby tester ports to the ruby cpu read and write ports
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/gem5/system/alpha/console/ |
H A D | dbmentry.S | 198 mov a0, t0 # cpu number 199 mov a1, t1 # cpu rpb pointer (virtual)
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H A D | console.c | 82 void SlaveLoop(int cpu); 189 0, /* 020: primary cpu id */ 204 sizeof(struct rpb_percpu), /* 098: per-cpu slot size. OVERRIDDEN */ 236 STATE_PV | STATE_PMV | STATE_PL), /* 080: per-cpu state bits */ 1035 SlaveCmd(int cpu, struct rpb_percpu *my_rpb) argument 1039 printf_lock("Slave CPU %d console command %s", cpu, 1057 SlaveLoop(int cpu) argument 1061 ((ulong)rpb_percpu + size * cpu); 1063 if (cpu == 0) { 1066 printf_lock("Entering slaveloop for cpu [all...] |
/gem5/src/cpu/ |
H A D | base.hh | 93 BaseCPU *cpu; member in class:CPUProgressEvent 117 // every cpu has an id, put it in the base cpu 123 /** Each cpu will have a socket ID that corresponds to its physical location 124 * in the system. This is usually used to bucket cpu cores under single DVFS 126 * cpu core grouping (as in the case of ARM via MPIDR register) 206 /** Get cpu task id */ 208 /** Set cpu task id */ 347 * @param cpu CPU to initialize read state from. 349 virtual void takeOverFrom(BaseCPU *cpu); [all...] |
/gem5/src/sim/ |
H A D | system.cc | 60 #include "cpu/kvm/base.hh" 61 #include "cpu/kvm/vm.hh" 63 #include "cpu/base.hh" 64 #include "cpu/thread_context.hh" 270 BaseCPU *cpu = tc->getCpuPtr(); local 271 if (cpu->waitForRemoteGDB()) { 273 cpu->name(), rgdb->port());
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