11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412831Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_ROB_HH__ 452292SN/A#define __CPU_O3_ROB_HH__ 461060SN/A 472292SN/A#include <string> 481461SN/A#include <utility> 491461SN/A#include <vector> 501060SN/A 518230Snate@binkert.org#include "arch/registers.hh" 528230Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 5413562Snikos.nikoleris@arm.com#include "enums/SMTQueuePolicy.hh" 556658Snate@binkert.org 569954SFaissal.Sleiman@arm.comstruct DerivO3CPUParams; 579954SFaissal.Sleiman@arm.com 581060SN/A/** 592292SN/A * ROB class. The ROB is largely what drives squashing. 601060SN/A */ 611061SN/Atemplate <class Impl> 621060SN/Aclass ROB 631060SN/A{ 641060SN/A public: 651060SN/A //Typedefs from the Impl. 662733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 671061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 681060SN/A 692292SN/A typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 702292SN/A typedef typename std::list<DynInstPtr>::iterator InstIt; 712292SN/A 722292SN/A /** Possible ROB statuses. */ 732292SN/A enum Status { 742292SN/A Running, 752292SN/A Idle, 762329SN/A ROBSquashing 772292SN/A }; 782292SN/A 792292SN/A private: 802292SN/A /** Per-thread ROB status. */ 812292SN/A Status robStatus[Impl::MaxThreads]; 822292SN/A 832292SN/A /** ROB resource sharing policy for SMT mode. */ 8413562Snikos.nikoleris@arm.com SMTQueuePolicy robPolicy; 851060SN/A 861060SN/A public: 871060SN/A /** ROB constructor. 889954SFaissal.Sleiman@arm.com * @param _cpu The cpu object pointer. 899954SFaissal.Sleiman@arm.com * @param params The cpu params including several ROB-specific parameters. 901060SN/A */ 919954SFaissal.Sleiman@arm.com ROB(O3CPU *_cpu, DerivO3CPUParams *params); 922292SN/A 932292SN/A std::string name() const; 941060SN/A 952292SN/A /** Sets pointer to the list of active threads. 962292SN/A * @param at_ptr Pointer to the list of active threads. 972292SN/A */ 986221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 992292SN/A 1009444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 1019444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 1022307SN/A 1032348SN/A /** Takes over another CPU's thread. */ 1042307SN/A void takeOverFrom(); 1052307SN/A 1062292SN/A /** Function to insert an instruction into the ROB. Note that whatever 1072292SN/A * calls this function must ensure that there is enough space within the 1082292SN/A * ROB for the new instruction. 1091763SN/A * @param inst The instruction being inserted into the ROB. 1101060SN/A */ 11113429Srekai.gonzalezalberquilla@arm.com void insertInst(const DynInstPtr &inst); 1121060SN/A 1131060SN/A /** Returns pointer to the head instruction within the ROB. There is 1141060SN/A * no guarantee as to the return value if the ROB is empty. 1151060SN/A * @retval Pointer to the DynInst that is at the head of the ROB. 1161060SN/A */ 1172329SN/A// DynInstPtr readHeadInst(); 1181060SN/A 1192292SN/A /** Returns a pointer to the head instruction of a specific thread within 1202292SN/A * the ROB. 1212292SN/A * @return Pointer to the DynInst that is at the head of the ROB. 1222292SN/A */ 12313429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &readHeadInst(ThreadID tid); 1241060SN/A 1258822Snilay@cs.wisc.edu /** Returns a pointer to the instruction with the given sequence if it is 1268822Snilay@cs.wisc.edu * in the ROB. 1278822Snilay@cs.wisc.edu */ 1288822Snilay@cs.wisc.edu DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst); 1298822Snilay@cs.wisc.edu 1302292SN/A /** Returns pointer to the tail instruction within the ROB. There is 1312292SN/A * no guarantee as to the return value if the ROB is empty. 1322292SN/A * @retval Pointer to the DynInst that is at the tail of the ROB. 1332292SN/A */ 1342329SN/A// DynInstPtr readTailInst(); 1351060SN/A 1362292SN/A /** Returns a pointer to the tail instruction of a specific thread within 1372292SN/A * the ROB. 1382292SN/A * @return Pointer to the DynInst that is at the tail of the ROB. 1392292SN/A */ 1406221Snate@binkert.org DynInstPtr readTailInst(ThreadID tid); 1411060SN/A 1422292SN/A /** Retires the head instruction, removing it from the ROB. */ 1432329SN/A// void retireHead(); 1442107SN/A 1452292SN/A /** Retires the head instruction of a specific thread, removing it from the 1462292SN/A * ROB. 1472292SN/A */ 1486221Snate@binkert.org void retireHead(ThreadID tid); 1492292SN/A 1502292SN/A /** Is the oldest instruction across all threads ready. */ 1512329SN/A// bool isHeadReady(); 1522107SN/A 1532292SN/A /** Is the oldest instruction across a particular thread ready. */ 1546221Snate@binkert.org bool isHeadReady(ThreadID tid); 1552292SN/A 1562292SN/A /** Is there any commitable head instruction across all threads ready. */ 1572292SN/A bool canCommit(); 1582292SN/A 1592292SN/A /** Re-adjust ROB partitioning. */ 1602292SN/A void resetEntries(); 1612292SN/A 1622292SN/A /** Number of entries needed For 'num_threads' amount of threads. */ 1636221Snate@binkert.org int entryAmount(ThreadID num_threads); 1642292SN/A 1652292SN/A /** Returns the number of total free entries in the ROB. */ 1661060SN/A unsigned numFreeEntries(); 1671060SN/A 1682292SN/A /** Returns the number of free entries in a specific ROB paritition. */ 1696221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 1702292SN/A 1712292SN/A /** Returns the maximum number of entries for a specific thread. */ 1726221Snate@binkert.org unsigned getMaxEntries(ThreadID tid) 1732292SN/A { return maxEntries[tid]; } 1742292SN/A 1752292SN/A /** Returns the number of entries being used by a specific thread. */ 1766221Snate@binkert.org unsigned getThreadEntries(ThreadID tid) 1772292SN/A { return threadEntries[tid]; } 1782292SN/A 1792292SN/A /** Returns if the ROB is full. */ 1801060SN/A bool isFull() 1811060SN/A { return numInstsInROB == numEntries; } 1821060SN/A 1832292SN/A /** Returns if a specific thread's partition is full. */ 1846221Snate@binkert.org bool isFull(ThreadID tid) 1852292SN/A { return threadEntries[tid] == numEntries; } 1862292SN/A 1872292SN/A /** Returns if the ROB is empty. */ 1889444SAndreas.Sandberg@ARM.com bool isEmpty() const 1891060SN/A { return numInstsInROB == 0; } 1901060SN/A 1912292SN/A /** Returns if a specific thread's partition is empty. */ 1929444SAndreas.Sandberg@ARM.com bool isEmpty(ThreadID tid) const 1932292SN/A { return threadEntries[tid] == 0; } 1941060SN/A 1952292SN/A /** Executes the squash, marking squashed instructions. */ 1966221Snate@binkert.org void doSquash(ThreadID tid); 1971060SN/A 1982292SN/A /** Squashes all instructions younger than the given sequence number for 1992292SN/A * the specific thread. 2002292SN/A */ 2016221Snate@binkert.org void squash(InstSeqNum squash_num, ThreadID tid); 2021060SN/A 2032292SN/A /** Updates the head instruction with the new oldest instruction. */ 2042292SN/A void updateHead(); 2051060SN/A 2062292SN/A /** Updates the tail instruction with the new youngest instruction. */ 2072292SN/A void updateTail(); 2081060SN/A 2092292SN/A /** Reads the PC of the oldest head instruction. */ 2102329SN/A// uint64_t readHeadPC(); 2111060SN/A 2122292SN/A /** Reads the PC of the head instruction of a specific thread. */ 2136221Snate@binkert.org// uint64_t readHeadPC(ThreadID tid); 2142292SN/A 2152292SN/A /** Reads the next PC of the oldest head instruction. */ 2162329SN/A// uint64_t readHeadNextPC(); 2172107SN/A 2182292SN/A /** Reads the next PC of the head instruction of a specific thread. */ 2196221Snate@binkert.org// uint64_t readHeadNextPC(ThreadID tid); 2202292SN/A 2212292SN/A /** Reads the sequence number of the oldest head instruction. */ 2222329SN/A// InstSeqNum readHeadSeqNum(); 2232107SN/A 2242292SN/A /** Reads the sequence number of the head instruction of a specific thread. 2252292SN/A */ 2266221Snate@binkert.org// InstSeqNum readHeadSeqNum(ThreadID tid); 2272292SN/A 2282292SN/A /** Reads the PC of the youngest tail instruction. */ 2292329SN/A// uint64_t readTailPC(); 2302107SN/A 2312292SN/A /** Reads the PC of the tail instruction of a specific thread. */ 2326221Snate@binkert.org// uint64_t readTailPC(ThreadID tid); 2332292SN/A 2342292SN/A /** Reads the sequence number of the youngest tail instruction. */ 2352329SN/A// InstSeqNum readTailSeqNum(); 2362107SN/A 2372292SN/A /** Reads the sequence number of tail instruction of a specific thread. */ 2386221Snate@binkert.org// InstSeqNum readTailSeqNum(ThreadID tid); 2391060SN/A 2401060SN/A /** Checks if the ROB is still in the process of squashing instructions. 2411060SN/A * @retval Whether or not the ROB is done squashing. 2421060SN/A */ 2436221Snate@binkert.org bool isDoneSquashing(ThreadID tid) const 2442292SN/A { return doneSquashing[tid]; } 2452292SN/A 2462292SN/A /** Checks if the ROB is still in the process of squashing instructions for 2472292SN/A * any thread. 2482292SN/A */ 2492292SN/A bool isDoneSquashing(); 2501060SN/A 2511060SN/A /** This is more of a debugging function than anything. Use 2521060SN/A * numInstsInROB to get the instructions in the ROB unless you are 2531060SN/A * double checking that variable. 2541060SN/A */ 2551060SN/A int countInsts(); 2561060SN/A 2572292SN/A /** This is more of a debugging function than anything. Use 2582292SN/A * threadEntries to get the instructions in the ROB unless you are 2592292SN/A * double checking that variable. 2602292SN/A */ 26114016SAndrea.Mondelli@ucf.edu size_t countInsts(ThreadID tid); 2622292SN/A 2637897Shestness@cs.utexas.edu /** Registers statistics. */ 2647897Shestness@cs.utexas.edu void regStats(); 2657897Shestness@cs.utexas.edu 2661060SN/A private: 2679444SAndreas.Sandberg@ARM.com /** Reset the ROB state */ 2689444SAndreas.Sandberg@ARM.com void resetState(); 2699444SAndreas.Sandberg@ARM.com 2701060SN/A /** Pointer to the CPU. */ 2712733Sktlim@umich.edu O3CPU *cpu; 2721060SN/A 2732292SN/A /** Active Threads in CPU */ 2746221Snate@binkert.org std::list<ThreadID> *activeThreads; 2752292SN/A 2761061SN/A /** Number of instructions in the ROB. */ 2771060SN/A unsigned numEntries; 2781060SN/A 2792292SN/A /** Entries Per Thread */ 2802292SN/A unsigned threadEntries[Impl::MaxThreads]; 2812292SN/A 2822292SN/A /** Max Insts a Thread Can Have in the ROB */ 2832292SN/A unsigned maxEntries[Impl::MaxThreads]; 2842292SN/A 2852292SN/A /** ROB List of Instructions */ 2862292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 2872292SN/A 2881060SN/A /** Number of instructions that can be squashed in a single cycle. */ 2891060SN/A unsigned squashWidth; 2901060SN/A 2912292SN/A public: 2921061SN/A /** Iterator pointing to the instruction which is the last instruction 2931061SN/A * in the ROB. This may at times be invalid (ie when the ROB is empty), 2941061SN/A * however it should never be incorrect. 2951061SN/A */ 2962292SN/A InstIt tail; 2971060SN/A 2982292SN/A /** Iterator pointing to the instruction which is the first instruction in 2992292SN/A * in the ROB*/ 3002292SN/A InstIt head; 3012292SN/A 3022292SN/A private: 3031061SN/A /** Iterator used for walking through the list of instructions when 3041061SN/A * squashing. Used so that there is persistent state between cycles; 3051061SN/A * when squashing, the instructions are marked as squashed but not 3061061SN/A * immediately removed, meaning the tail iterator remains the same before 3071061SN/A * and after a squash. 3081061SN/A * This will always be set to cpu->instList.end() if it is invalid. 3091061SN/A */ 3102292SN/A InstIt squashIt[Impl::MaxThreads]; 3111060SN/A 3122292SN/A public: 3131061SN/A /** Number of instructions in the ROB. */ 3141060SN/A int numInstsInROB; 3151060SN/A 3162348SN/A /** Dummy instruction returned if there are no insts left. */ 3172292SN/A DynInstPtr dummyInst; 3182292SN/A 3192292SN/A private: 3201060SN/A /** The sequence number of the squashed instruction. */ 3212877Sksewell@umich.edu InstSeqNum squashedSeqNum[Impl::MaxThreads]; 3221060SN/A 3231060SN/A /** Is the ROB done squashing. */ 3242292SN/A bool doneSquashing[Impl::MaxThreads]; 3252292SN/A 3262292SN/A /** Number of active threads. */ 3276221Snate@binkert.org ThreadID numThreads; 3287897Shestness@cs.utexas.edu 3297897Shestness@cs.utexas.edu // The number of rob_reads 3307897Shestness@cs.utexas.edu Stats::Scalar robReads; 3317897Shestness@cs.utexas.edu // The number of rob_writes 3327897Shestness@cs.utexas.edu Stats::Scalar robWrites; 3331060SN/A}; 3341060SN/A 3352292SN/A#endif //__CPU_O3_ROB_HH__ 336