11689SN/A/*
29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited
39444SAndreas.Sandberg@ARM.com * All rights reserved
49444SAndreas.Sandberg@ARM.com *
59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall
69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual
79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating
89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software
99444SAndreas.Sandberg@ARM.com * licensed hereunder.  You may use the software subject to the license
109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated
119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software,
129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form.
139444SAndreas.Sandberg@ARM.com *
142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
151689SN/A * All rights reserved.
161689SN/A *
171689SN/A * Redistribution and use in source and binary forms, with or without
181689SN/A * modification, are permitted provided that the following conditions are
191689SN/A * met: redistributions of source code must retain the above copyright
201689SN/A * notice, this list of conditions and the following disclaimer;
211689SN/A * redistributions in binary form must reproduce the above copyright
221689SN/A * notice, this list of conditions and the following disclaimer in the
231689SN/A * documentation and/or other materials provided with the distribution;
241689SN/A * neither the name of the copyright holders nor the names of its
251689SN/A * contributors may be used to endorse or promote products derived from
261689SN/A * this software without specific prior written permission.
271689SN/A *
281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665Ssaidi@eecs.umich.edu *
402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
412831Sksewell@umich.edu *          Korey Sewell
421689SN/A */
431689SN/A
449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_ROB_IMPL_HH__
459944Smatt.horsnell@ARM.com#define __CPU_O3_ROB_IMPL_HH__
469944Smatt.horsnell@ARM.com
476221Snate@binkert.org#include <list>
486221Snate@binkert.org
4913449Sgabeblack@google.com#include "base/logging.hh"
501717SN/A#include "cpu/o3/rob.hh"
518232Snate@binkert.org#include "debug/Fetch.hh"
528232Snate@binkert.org#include "debug/ROB.hh"
539954SFaissal.Sleiman@arm.com#include "params/DerivO3CPU.hh"
541060SN/A
556221Snate@binkert.orgusing namespace std;
562292SN/A
571061SN/Atemplate <class Impl>
589954SFaissal.Sleiman@arm.comROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params)
5913562Snikos.nikoleris@arm.com    : robPolicy(params->smtROBPolicy),
6013562Snikos.nikoleris@arm.com      cpu(_cpu),
619954SFaissal.Sleiman@arm.com      numEntries(params->numROBEntries),
629954SFaissal.Sleiman@arm.com      squashWidth(params->squashWidth),
631060SN/A      numInstsInROB(0),
649954SFaissal.Sleiman@arm.com      numThreads(params->numThreads)
651060SN/A{
662292SN/A    //Figure out rob policy
6713562Snikos.nikoleris@arm.com    if (robPolicy == SMTQueuePolicy::Dynamic) {
682292SN/A        //Set Max Entries to Total ROB Capacity
696221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
706221Snate@binkert.org            maxEntries[tid] = numEntries;
712292SN/A        }
722292SN/A
7313562Snikos.nikoleris@arm.com    } else if (robPolicy == SMTQueuePolicy::Partitioned) {
744329Sktlim@umich.edu        DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
752292SN/A
762292SN/A        //@todo:make work if part_amt doesnt divide evenly.
772292SN/A        int part_amt = numEntries / numThreads;
782292SN/A
792292SN/A        //Divide ROB up evenly
806221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
816221Snate@binkert.org            maxEntries[tid] = part_amt;
822292SN/A        }
832292SN/A
8413562Snikos.nikoleris@arm.com    } else if (robPolicy == SMTQueuePolicy::Threshold) {
854329Sktlim@umich.edu        DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
862292SN/A
879954SFaissal.Sleiman@arm.com        int threshold =  params->smtROBThreshold;;
882292SN/A
892292SN/A        //Divide up by threshold amount
906221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
916221Snate@binkert.org            maxEntries[tid] = threshold;
922292SN/A        }
932292SN/A    }
9413562Snikos.nikoleris@arm.com
9513453Srekai.gonzalezalberquilla@arm.com    for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
9613453Srekai.gonzalezalberquilla@arm.com        maxEntries[tid] = 0;
9713453Srekai.gonzalezalberquilla@arm.com    }
981060SN/A
999444SAndreas.Sandberg@ARM.com    resetState();
1009444SAndreas.Sandberg@ARM.com}
1019444SAndreas.Sandberg@ARM.com
1029444SAndreas.Sandberg@ARM.comtemplate <class Impl>
1039444SAndreas.Sandberg@ARM.comvoid
1049444SAndreas.Sandberg@ARM.comROB<Impl>::resetState()
1059444SAndreas.Sandberg@ARM.com{
10613453Srekai.gonzalezalberquilla@arm.com    for (ThreadID tid = 0; tid  < Impl::MaxThreads; tid++) {
1079444SAndreas.Sandberg@ARM.com        threadEntries[tid] = 0;
1086221Snate@binkert.org        squashIt[tid] = instList[tid].end();
1099444SAndreas.Sandberg@ARM.com        squashedSeqNum[tid] = 0;
11013453Srekai.gonzalezalberquilla@arm.com        doneSquashing[tid] = true;
1112292SN/A    }
1129444SAndreas.Sandberg@ARM.com    numInstsInROB = 0;
1131060SN/A
1142292SN/A    // Initialize the "universal" ROB head & tail point to invalid
1152292SN/A    // pointers
1162292SN/A    head = instList[0].end();
1172292SN/A    tail = instList[0].end();
1182292SN/A}
1192292SN/A
1202292SN/Atemplate <class Impl>
1214329Sktlim@umich.edustd::string
1224329Sktlim@umich.eduROB<Impl>::name() const
1234329Sktlim@umich.edu{
1244329Sktlim@umich.edu    return cpu->name() + ".rob";
1254329Sktlim@umich.edu}
1264329Sktlim@umich.edu
1274329Sktlim@umich.edutemplate <class Impl>
1282292SN/Avoid
1296221Snate@binkert.orgROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
1302292SN/A{
1312292SN/A    DPRINTF(ROB, "Setting active threads list pointer.\n");
1322292SN/A    activeThreads = at_ptr;
1332292SN/A}
1342292SN/A
1352307SN/Atemplate <class Impl>
1362307SN/Avoid
1379444SAndreas.Sandberg@ARM.comROB<Impl>::drainSanityCheck() const
1382307SN/A{
1399444SAndreas.Sandberg@ARM.com    for (ThreadID tid = 0; tid  < numThreads; tid++)
1409444SAndreas.Sandberg@ARM.com        assert(instList[tid].empty());
1419444SAndreas.Sandberg@ARM.com    assert(isEmpty());
1422307SN/A}
1432307SN/A
1442307SN/Atemplate <class Impl>
1452307SN/Avoid
1462307SN/AROB<Impl>::takeOverFrom()
1472307SN/A{
1489444SAndreas.Sandberg@ARM.com    resetState();
1492307SN/A}
1502292SN/A
1512292SN/Atemplate <class Impl>
1522292SN/Avoid
1532292SN/AROB<Impl>::resetEntries()
1542292SN/A{
15513562Snikos.nikoleris@arm.com    if (robPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) {
15614016SAndrea.Mondelli@ucf.edu        auto active_threads = activeThreads->size();
1572292SN/A
1586221Snate@binkert.org        list<ThreadID>::iterator threads = activeThreads->begin();
1596221Snate@binkert.org        list<ThreadID>::iterator end = activeThreads->end();
1602292SN/A
1613867Sbinkertn@umich.edu        while (threads != end) {
1626221Snate@binkert.org            ThreadID tid = *threads++;
1633867Sbinkertn@umich.edu
16413562Snikos.nikoleris@arm.com            if (robPolicy == SMTQueuePolicy::Partitioned) {
1653867Sbinkertn@umich.edu                maxEntries[tid] = numEntries / active_threads;
16613562Snikos.nikoleris@arm.com            } else if (robPolicy == SMTQueuePolicy::Threshold &&
16713562Snikos.nikoleris@arm.com                       active_threads == 1) {
1683867Sbinkertn@umich.edu                maxEntries[tid] = numEntries;
1692292SN/A            }
1702292SN/A        }
1712292SN/A    }
1722292SN/A}
1732292SN/A
1742292SN/Atemplate <class Impl>
1752292SN/Aint
1766221Snate@binkert.orgROB<Impl>::entryAmount(ThreadID num_threads)
1772292SN/A{
17813562Snikos.nikoleris@arm.com    if (robPolicy == SMTQueuePolicy::Partitioned) {
1792292SN/A        return numEntries / num_threads;
1802292SN/A    } else {
1812292SN/A        return 0;
1822292SN/A    }
1831060SN/A}
1841060SN/A
1851061SN/Atemplate <class Impl>
1861060SN/Aint
1871060SN/AROB<Impl>::countInsts()
1881060SN/A{
1896221Snate@binkert.org    int total = 0;
1901061SN/A
1916221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++)
1926221Snate@binkert.org        total += countInsts(tid);
1931060SN/A
1942292SN/A    return total;
1952292SN/A}
1961060SN/A
1972292SN/Atemplate <class Impl>
19814016SAndrea.Mondelli@ucf.edusize_t
1996221Snate@binkert.orgROB<Impl>::countInsts(ThreadID tid)
2002292SN/A{
2012292SN/A    return instList[tid].size();
2021060SN/A}
2031060SN/A
2041061SN/Atemplate <class Impl>
2051060SN/Avoid
20613429Srekai.gonzalezalberquilla@arm.comROB<Impl>::insertInst(const DynInstPtr &inst)
2071060SN/A{
2081060SN/A    assert(inst);
2091060SN/A
2107897Shestness@cs.utexas.edu    robWrites++;
2117897Shestness@cs.utexas.edu
2127720Sgblack@eecs.umich.edu    DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState());
2131060SN/A
2141060SN/A    assert(numInstsInROB != numEntries);
2151060SN/A
2166221Snate@binkert.org    ThreadID tid = inst->threadNumber;
2171060SN/A
2182292SN/A    instList[tid].push_back(inst);
2192292SN/A
2202292SN/A    //Set Up head iterator if this is the 1st instruction in the ROB
2212292SN/A    if (numInstsInROB == 0) {
2222292SN/A        head = instList[tid].begin();
2232292SN/A        assert((*head) == inst);
2241060SN/A    }
2251060SN/A
2262292SN/A    //Must Decrement for iterator to actually be valid  since __.end()
2272292SN/A    //actually points to 1 after the last inst
2282292SN/A    tail = instList[tid].end();
2292292SN/A    tail--;
2302292SN/A
2312292SN/A    inst->setInROB();
2322292SN/A
2332292SN/A    ++numInstsInROB;
2342292SN/A    ++threadEntries[tid];
2352292SN/A
2361060SN/A    assert((*tail) == inst);
2371060SN/A
2382292SN/A    DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]);
2391060SN/A}
2401060SN/A
2412292SN/Atemplate <class Impl>
2422292SN/Avoid
2436221Snate@binkert.orgROB<Impl>::retireHead(ThreadID tid)
2442292SN/A{
2457897Shestness@cs.utexas.edu    robWrites++;
2467897Shestness@cs.utexas.edu
2471061SN/A    assert(numInstsInROB > 0);
2481060SN/A
24913429Srekai.gonzalezalberquilla@arm.com    // Get the head ROB instruction by copying it and remove it from the list
2502292SN/A    InstIt head_it = instList[tid].begin();
2511060SN/A
25213429Srekai.gonzalezalberquilla@arm.com    DynInstPtr head_inst = std::move(*head_it);
25313429Srekai.gonzalezalberquilla@arm.com    instList[tid].erase(head_it);
2541858SN/A
2551060SN/A    assert(head_inst->readyToCommit());
2561060SN/A
25713831SAndrea.Mondelli@ucf.edu    DPRINTF(ROB, "[tid:%i] Retiring head instruction, "
25813831SAndrea.Mondelli@ucf.edu            "instruction PC %s, [sn:%llu]\n", tid, head_inst->pcState(),
2591060SN/A            head_inst->seqNum);
2601060SN/A
2611060SN/A    --numInstsInROB;
2622292SN/A    --threadEntries[tid];
2631060SN/A
2642731Sktlim@umich.edu    head_inst->clearInROB();
2652292SN/A    head_inst->setCommitted();
2662292SN/A
2672292SN/A    //Update "Global" Head of ROB
2682292SN/A    updateHead();
2692292SN/A
2702329SN/A    // @todo: A special case is needed if the instruction being
2712329SN/A    // retired is the only instruction in the ROB; otherwise the tail
2722329SN/A    // iterator will become invalidated.
2731681SN/A    cpu->removeFrontInst(head_inst);
2741060SN/A}
2752292SN/A
2762292SN/Atemplate <class Impl>
2772292SN/Abool
2786221Snate@binkert.orgROB<Impl>::isHeadReady(ThreadID tid)
2792292SN/A{
2807897Shestness@cs.utexas.edu    robReads++;
2812292SN/A    if (threadEntries[tid] != 0) {
2822292SN/A        return instList[tid].front()->readyToCommit();
2832292SN/A    }
2842292SN/A
2852292SN/A    return false;
2862292SN/A}
2872292SN/A
2882292SN/Atemplate <class Impl>
2892292SN/Abool
2902292SN/AROB<Impl>::canCommit()
2912292SN/A{
2922292SN/A    //@todo: set ActiveThreads through ROB or CPU
2936221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
2946221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
2952292SN/A
2963867Sbinkertn@umich.edu    while (threads != end) {
2976221Snate@binkert.org        ThreadID tid = *threads++;
2982292SN/A
2992292SN/A        if (isHeadReady(tid)) {
3002292SN/A            return true;
3012292SN/A        }
3021060SN/A    }
3031060SN/A
3041060SN/A    return false;
3051060SN/A}
3061060SN/A
3071061SN/Atemplate <class Impl>
3081060SN/Aunsigned
3091060SN/AROB<Impl>::numFreeEntries()
3101060SN/A{
3111060SN/A    return numEntries - numInstsInROB;
3121060SN/A}
3131060SN/A
3141061SN/Atemplate <class Impl>
3152292SN/Aunsigned
3166221Snate@binkert.orgROB<Impl>::numFreeEntries(ThreadID tid)
3171060SN/A{
3182292SN/A    return maxEntries[tid] - threadEntries[tid];
3191060SN/A}
3201060SN/A
3211061SN/Atemplate <class Impl>
3221060SN/Avoid
3236221Snate@binkert.orgROB<Impl>::doSquash(ThreadID tid)
3241060SN/A{
3257897Shestness@cs.utexas.edu    robWrites++;
32613831SAndrea.Mondelli@ucf.edu    DPRINTF(ROB, "[tid:%i] Squashing instructions until [sn:%llu].\n",
3272877Sksewell@umich.edu            tid, squashedSeqNum[tid]);
3281858SN/A
3292292SN/A    assert(squashIt[tid] != instList[tid].end());
3302292SN/A
3312877Sksewell@umich.edu    if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) {
33213831SAndrea.Mondelli@ucf.edu        DPRINTF(ROB, "[tid:%i] Done squashing instructions.\n",
3332292SN/A                tid);
3342292SN/A
3352292SN/A        squashIt[tid] = instList[tid].end();
3362292SN/A
3372292SN/A        doneSquashing[tid] = true;
3382292SN/A        return;
3392292SN/A    }
3402292SN/A
3412292SN/A    bool robTailUpdate = false;
3421858SN/A
3431858SN/A    for (int numSquashed = 0;
3442292SN/A         numSquashed < squashWidth &&
3452292SN/A         squashIt[tid] != instList[tid].end() &&
3462877Sksewell@umich.edu         (*squashIt[tid])->seqNum > squashedSeqNum[tid];
3471858SN/A         ++numSquashed)
3481858SN/A    {
34913831SAndrea.Mondelli@ucf.edu        DPRINTF(ROB, "[tid:%i] Squashing instruction PC %s, seq num %i.\n",
3502292SN/A                (*squashIt[tid])->threadNumber,
3517720Sgblack@eecs.umich.edu                (*squashIt[tid])->pcState(),
3522292SN/A                (*squashIt[tid])->seqNum);
3531858SN/A
3541858SN/A        // Mark the instruction as squashed, and ready to commit so that
3551858SN/A        // it can drain out of the pipeline.
3562292SN/A        (*squashIt[tid])->setSquashed();
3571858SN/A
3582292SN/A        (*squashIt[tid])->setCanCommit();
3591858SN/A
3602292SN/A
3612292SN/A        if (squashIt[tid] == instList[tid].begin()) {
3622292SN/A            DPRINTF(ROB, "Reached head of instruction list while "
3631858SN/A                    "squashing.\n");
3641858SN/A
3652292SN/A            squashIt[tid] = instList[tid].end();
3661858SN/A
3672292SN/A            doneSquashing[tid] = true;
3681858SN/A
3691858SN/A            return;
3701858SN/A        }
3711858SN/A
3722292SN/A        InstIt tail_thread = instList[tid].end();
3732292SN/A        tail_thread--;
3742292SN/A
3752292SN/A        if ((*squashIt[tid]) == (*tail_thread))
3762292SN/A            robTailUpdate = true;
3772292SN/A
3782292SN/A        squashIt[tid]--;
3791858SN/A    }
3801858SN/A
3811858SN/A
3821858SN/A    // Check if ROB is done squashing.
3832877Sksewell@umich.edu    if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) {
38413831SAndrea.Mondelli@ucf.edu        DPRINTF(ROB, "[tid:%i] Done squashing instructions.\n",
3852292SN/A                tid);
3861858SN/A
3872292SN/A        squashIt[tid] = instList[tid].end();
3881858SN/A
3892292SN/A        doneSquashing[tid] = true;
3902292SN/A    }
3912292SN/A
3922292SN/A    if (robTailUpdate) {
3932292SN/A        updateTail();
3942292SN/A    }
3952292SN/A}
3962292SN/A
3972292SN/A
3982292SN/Atemplate <class Impl>
3992292SN/Avoid
4002292SN/AROB<Impl>::updateHead()
4012292SN/A{
4022292SN/A    InstSeqNum lowest_num = 0;
4032292SN/A    bool first_valid = true;
4042292SN/A
4052292SN/A    // @todo: set ActiveThreads through ROB or CPU
4066221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
4076221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
4082292SN/A
4093867Sbinkertn@umich.edu    while (threads != end) {
4106221Snate@binkert.org        ThreadID tid = *threads++;
4112292SN/A
4123867Sbinkertn@umich.edu        if (instList[tid].empty())
4132292SN/A            continue;
4142292SN/A
4152292SN/A        if (first_valid) {
4163867Sbinkertn@umich.edu            head = instList[tid].begin();
4172292SN/A            lowest_num = (*head)->seqNum;
4182292SN/A            first_valid = false;
4192292SN/A            continue;
4202292SN/A        }
4212292SN/A
4223867Sbinkertn@umich.edu        InstIt head_thread = instList[tid].begin();
4232292SN/A
4242292SN/A        DynInstPtr head_inst = (*head_thread);
4252292SN/A
4262292SN/A        assert(head_inst != 0);
4272292SN/A
4282292SN/A        if (head_inst->seqNum < lowest_num) {
4292292SN/A            head = head_thread;
4302292SN/A            lowest_num = head_inst->seqNum;
4312292SN/A        }
4322292SN/A    }
4332292SN/A
4342292SN/A    if (first_valid) {
4352292SN/A        head = instList[0].end();
4362292SN/A    }
4372292SN/A
4382292SN/A}
4392292SN/A
4402292SN/Atemplate <class Impl>
4412292SN/Avoid
4422292SN/AROB<Impl>::updateTail()
4432292SN/A{
4442292SN/A    tail = instList[0].end();
4452292SN/A    bool first_valid = true;
4462292SN/A
4476221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
4486221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
4492292SN/A
4503867Sbinkertn@umich.edu    while (threads != end) {
4516221Snate@binkert.org        ThreadID tid = *threads++;
4522292SN/A
4532292SN/A        if (instList[tid].empty()) {
4542292SN/A            continue;
4552292SN/A        }
4562292SN/A
4572292SN/A        // If this is the first valid then assign w/out
4582292SN/A        // comparison
4592292SN/A        if (first_valid) {
4602292SN/A            tail = instList[tid].end();
4612292SN/A            tail--;
4622292SN/A            first_valid = false;
4632292SN/A            continue;
4642292SN/A        }
4652292SN/A
4662292SN/A        // Assign new tail if this thread's tail is younger
4672292SN/A        // than our current "tail high"
4682292SN/A        InstIt tail_thread = instList[tid].end();
4692292SN/A        tail_thread--;
4702292SN/A
4712292SN/A        if ((*tail_thread)->seqNum > (*tail)->seqNum) {
4722292SN/A            tail = tail_thread;
4732292SN/A        }
4742292SN/A    }
4752292SN/A}
4762292SN/A
4772292SN/A
4782292SN/Atemplate <class Impl>
4792292SN/Avoid
4806221Snate@binkert.orgROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid)
4812292SN/A{
48210164Ssleimanf@umich.edu    if (isEmpty(tid)) {
4832292SN/A        DPRINTF(ROB, "Does not need to squash due to being empty "
48413831SAndrea.Mondelli@ucf.edu                "[sn:%llu]\n",
4852292SN/A                squash_num);
4862292SN/A
4872292SN/A        return;
4882292SN/A    }
4892292SN/A
4902292SN/A    DPRINTF(ROB, "Starting to squash within the ROB.\n");
4912292SN/A
4922292SN/A    robStatus[tid] = ROBSquashing;
4932292SN/A
4942292SN/A    doneSquashing[tid] = false;
4951060SN/A
4962877Sksewell@umich.edu    squashedSeqNum[tid] = squash_num;
4971060SN/A
4982292SN/A    if (!instList[tid].empty()) {
4992292SN/A        InstIt tail_thread = instList[tid].end();
5002292SN/A        tail_thread--;
5011060SN/A
5022292SN/A        squashIt[tid] = tail_thread;
5031060SN/A
5042292SN/A        doSquash(tid);
5051858SN/A    }
5061060SN/A}
5072877Sksewell@umich.edu
5082292SN/Atemplate <class Impl>
50913429Srekai.gonzalezalberquilla@arm.comconst typename Impl::DynInstPtr&
5106221Snate@binkert.orgROB<Impl>::readHeadInst(ThreadID tid)
5112292SN/A{
5122292SN/A    if (threadEntries[tid] != 0) {
5132292SN/A        InstIt head_thread = instList[tid].begin();
5141060SN/A
51510231Ssteve.reinhardt@amd.com        assert((*head_thread)->isInROB());
5161858SN/A
5172292SN/A        return *head_thread;
5182292SN/A    } else {
5192292SN/A        return dummyInst;
5202292SN/A    }
5211858SN/A}
5222877Sksewell@umich.edu
5232292SN/Atemplate <class Impl>
5242292SN/Atypename Impl::DynInstPtr
5256221Snate@binkert.orgROB<Impl>::readTailInst(ThreadID tid)
5262292SN/A{
5272292SN/A    InstIt tail_thread = instList[tid].end();
5282292SN/A    tail_thread--;
5292292SN/A
5302292SN/A    return *tail_thread;
5312292SN/A}
5322292SN/A
5337897Shestness@cs.utexas.edutemplate <class Impl>
5347897Shestness@cs.utexas.eduvoid
5357897Shestness@cs.utexas.eduROB<Impl>::regStats()
5367897Shestness@cs.utexas.edu{
5377897Shestness@cs.utexas.edu    using namespace Stats;
5387897Shestness@cs.utexas.edu    robReads
5397897Shestness@cs.utexas.edu        .name(name() + ".rob_reads")
5407897Shestness@cs.utexas.edu        .desc("The number of ROB reads");
5417897Shestness@cs.utexas.edu
5427897Shestness@cs.utexas.edu    robWrites
5437897Shestness@cs.utexas.edu        .name(name() + ".rob_writes")
5447897Shestness@cs.utexas.edu        .desc("The number of ROB writes");
5457897Shestness@cs.utexas.edu}
5467897Shestness@cs.utexas.edu
5478822Snilay@cs.wisc.edutemplate <class Impl>
5488822Snilay@cs.wisc.edutypename Impl::DynInstPtr
5498822Snilay@cs.wisc.eduROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst)
5508822Snilay@cs.wisc.edu{
5518822Snilay@cs.wisc.edu    for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) {
5528822Snilay@cs.wisc.edu        if ((*it)->seqNum == squash_inst) {
5538822Snilay@cs.wisc.edu            return *it;
5548822Snilay@cs.wisc.edu        }
5558822Snilay@cs.wisc.edu    }
5568822Snilay@cs.wisc.edu    return NULL;
5578822Snilay@cs.wisc.edu}
5589944Smatt.horsnell@ARM.com
5599944Smatt.horsnell@ARM.com#endif//__CPU_O3_ROB_IMPL_HH__
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