11689SN/A/* 214025Sgiacomo.gabrielli@arm.com * Copyright (c) 2010-2012, 2014-2019 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_RENAME_IMPL_HH__ 479944Smatt.horsnell@ARM.com 481060SN/A#include <list> 491060SN/A 503773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 531717SN/A#include "cpu/o3/rename.hh" 549913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Rename.hh" 579527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 585529Snate@binkert.org#include "params/DerivO3CPU.hh" 591060SN/A 606221Snate@binkert.orgusing namespace std; 616221Snate@binkert.org 621061SN/Atemplate <class Impl> 635529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 644329Sktlim@umich.edu : cpu(_cpu), 654329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 662292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 672292SN/A commitToRenameDelay(params->commitToRenameDelay), 682292SN/A renameWidth(params->renameWidth), 692292SN/A commitWidth(params->commitWidth), 7012109SRekai.GonzalezAlberquilla@arm.com numThreads(params->numThreads) 711060SN/A{ 7210172Sdam.sunwoo@arm.com if (renameWidth > Impl::MaxWidth) 7310172Sdam.sunwoo@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7510172Sdam.sunwoo@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7610172Sdam.sunwoo@arm.com 772292SN/A // @todo: Make into a parameter. 7810328Smitch.hayenga@arm.com skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 7913453Srekai.gonzalezalberquilla@arm.com for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) { 8013453Srekai.gonzalezalberquilla@arm.com renameStatus[tid] = Idle; 8113453Srekai.gonzalezalberquilla@arm.com renameMap[tid] = nullptr; 8213453Srekai.gonzalezalberquilla@arm.com instsInProgress[tid] = 0; 8313453Srekai.gonzalezalberquilla@arm.com loadsInProgress[tid] = 0; 8413453Srekai.gonzalezalberquilla@arm.com storesInProgress[tid] = 0; 8513453Srekai.gonzalezalberquilla@arm.com freeEntries[tid] = {0, 0, 0, 0}; 8613453Srekai.gonzalezalberquilla@arm.com emptyROB[tid] = true; 8713453Srekai.gonzalezalberquilla@arm.com stalls[tid] = {false, false}; 8813453Srekai.gonzalezalberquilla@arm.com serializeInst[tid] = nullptr; 8913453Srekai.gonzalezalberquilla@arm.com serializeOnNextInst[tid] = false; 9013453Srekai.gonzalezalberquilla@arm.com } 912292SN/A} 922292SN/A 932292SN/Atemplate <class Impl> 942292SN/Astd::string 952292SN/ADefaultRename<Impl>::name() const 962292SN/A{ 972292SN/A return cpu->name() + ".rename"; 981060SN/A} 991060SN/A 1001061SN/Atemplate <class Impl> 1011060SN/Avoid 1022292SN/ADefaultRename<Impl>::regStats() 1031062SN/A{ 1041062SN/A renameSquashCycles 1058240Snate@binkert.org .name(name() + ".SquashCycles") 1061062SN/A .desc("Number of cycles rename is squashing") 1071062SN/A .prereq(renameSquashCycles); 1081062SN/A renameIdleCycles 1098240Snate@binkert.org .name(name() + ".IdleCycles") 1101062SN/A .desc("Number of cycles rename is idle") 1111062SN/A .prereq(renameIdleCycles); 1121062SN/A renameBlockCycles 1138240Snate@binkert.org .name(name() + ".BlockCycles") 1141062SN/A .desc("Number of cycles rename is blocking") 1151062SN/A .prereq(renameBlockCycles); 1162301SN/A renameSerializeStallCycles 1178240Snate@binkert.org .name(name() + ".serializeStallCycles") 1182301SN/A .desc("count of cycles rename stalled for serializing inst") 1192301SN/A .flags(Stats::total); 1202292SN/A renameRunCycles 1218240Snate@binkert.org .name(name() + ".RunCycles") 1222292SN/A .desc("Number of cycles rename is running") 1232292SN/A .prereq(renameIdleCycles); 1241062SN/A renameUnblockCycles 1258240Snate@binkert.org .name(name() + ".UnblockCycles") 1261062SN/A .desc("Number of cycles rename is unblocking") 1271062SN/A .prereq(renameUnblockCycles); 1281062SN/A renameRenamedInsts 1298240Snate@binkert.org .name(name() + ".RenamedInsts") 1301062SN/A .desc("Number of instructions processed by rename") 1311062SN/A .prereq(renameRenamedInsts); 1321062SN/A renameSquashedInsts 1338240Snate@binkert.org .name(name() + ".SquashedInsts") 1341062SN/A .desc("Number of squashed instructions processed by rename") 1351062SN/A .prereq(renameSquashedInsts); 1361062SN/A renameROBFullEvents 1378240Snate@binkert.org .name(name() + ".ROBFullEvents") 1382292SN/A .desc("Number of times rename has blocked due to ROB full") 1391062SN/A .prereq(renameROBFullEvents); 1401062SN/A renameIQFullEvents 1418240Snate@binkert.org .name(name() + ".IQFullEvents") 1422292SN/A .desc("Number of times rename has blocked due to IQ full") 1431062SN/A .prereq(renameIQFullEvents); 14410239Sbinhpham@cs.rutgers.edu renameLQFullEvents 14510239Sbinhpham@cs.rutgers.edu .name(name() + ".LQFullEvents") 14610239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to LQ full") 14710239Sbinhpham@cs.rutgers.edu .prereq(renameLQFullEvents); 14810239Sbinhpham@cs.rutgers.edu renameSQFullEvents 14910239Sbinhpham@cs.rutgers.edu .name(name() + ".SQFullEvents") 15010239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to SQ full") 15110239Sbinhpham@cs.rutgers.edu .prereq(renameSQFullEvents); 1521062SN/A renameFullRegistersEvents 1538240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1541062SN/A .desc("Number of times there has been no free registers") 1551062SN/A .prereq(renameFullRegistersEvents); 1561062SN/A renameRenamedOperands 1578240Snate@binkert.org .name(name() + ".RenamedOperands") 1581062SN/A .desc("Number of destination operands rename has renamed") 1591062SN/A .prereq(renameRenamedOperands); 1601062SN/A renameRenameLookups 1618240Snate@binkert.org .name(name() + ".RenameLookups") 1621062SN/A .desc("Number of register rename lookups that rename has made") 1631062SN/A .prereq(renameRenameLookups); 1641062SN/A renameCommittedMaps 1658240Snate@binkert.org .name(name() + ".CommittedMaps") 1661062SN/A .desc("Number of HB maps that are committed") 1671062SN/A .prereq(renameCommittedMaps); 1681062SN/A renameUndoneMaps 1698240Snate@binkert.org .name(name() + ".UndoneMaps") 1701062SN/A .desc("Number of HB maps that are undone due to squashing") 1711062SN/A .prereq(renameUndoneMaps); 1722301SN/A renamedSerializing 1738240Snate@binkert.org .name(name() + ".serializingInsts") 1742301SN/A .desc("count of serializing insts renamed") 1752301SN/A .flags(Stats::total) 1762301SN/A ; 1772301SN/A renamedTempSerializing 1788240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1792301SN/A .desc("count of temporary serializing insts renamed") 1802301SN/A .flags(Stats::total) 1812301SN/A ; 1822307SN/A renameSkidInsts 1838240Snate@binkert.org .name(name() + ".skidInsts") 1842307SN/A .desc("count of insts added to the skid buffer") 1852307SN/A .flags(Stats::total) 1862307SN/A ; 1877897Shestness@cs.utexas.edu intRenameLookups 1888240Snate@binkert.org .name(name() + ".int_rename_lookups") 1897897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1907897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1917897Shestness@cs.utexas.edu fpRenameLookups 1928240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1937897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1947897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 19512109SRekai.GonzalezAlberquilla@arm.com vecRenameLookups 19612109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_rename_lookups") 19712109SRekai.GonzalezAlberquilla@arm.com .desc("Number of vector rename lookups") 19812109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRenameLookups); 19913610Sgiacomo.gabrielli@arm.com vecPredRenameLookups 20013610Sgiacomo.gabrielli@arm.com .name(name() + ".vec_pred_rename_lookups") 20113610Sgiacomo.gabrielli@arm.com .desc("Number of vector predicate rename lookups") 20213610Sgiacomo.gabrielli@arm.com .prereq(vecPredRenameLookups); 2031062SN/A} 2041062SN/A 2051062SN/Atemplate <class Impl> 2061062SN/Avoid 20711246Sradhika.jagtap@ARM.comDefaultRename<Impl>::regProbePoints() 20811246Sradhika.jagtap@ARM.com{ 20911246Sradhika.jagtap@ARM.com ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 21011246Sradhika.jagtap@ARM.com ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 21111246Sradhika.jagtap@ARM.com "SquashInRename"); 21211246Sradhika.jagtap@ARM.com} 21311246Sradhika.jagtap@ARM.com 21411246Sradhika.jagtap@ARM.comtemplate <class Impl> 21511246Sradhika.jagtap@ARM.comvoid 2162292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2171060SN/A{ 2181060SN/A timeBuffer = tb_ptr; 2191060SN/A 2201060SN/A // Setup wire to read information from time buffer, from IEW stage. 2211060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2221060SN/A 2231060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2241060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2251060SN/A 2261060SN/A // Setup wire to write information to previous stages. 2271060SN/A toDecode = timeBuffer->getWire(0); 2281060SN/A} 2291060SN/A 2301061SN/Atemplate <class Impl> 2311060SN/Avoid 2322292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2331060SN/A{ 2341060SN/A renameQueue = rq_ptr; 2351060SN/A 2361060SN/A // Setup wire to write information to future stages. 2371060SN/A toIEW = renameQueue->getWire(0); 2381060SN/A} 2391060SN/A 2401061SN/Atemplate <class Impl> 2411060SN/Avoid 2422292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2431060SN/A{ 2441060SN/A decodeQueue = dq_ptr; 2451060SN/A 2461060SN/A // Setup wire to get information from decode. 2471060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2481060SN/A} 2491060SN/A 2501061SN/Atemplate <class Impl> 2511060SN/Avoid 2529427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2531060SN/A{ 2549444SAndreas.Sandberg@ARM.com resetStage(); 2559444SAndreas.Sandberg@ARM.com} 2569444SAndreas.Sandberg@ARM.com 2579444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2589444SAndreas.Sandberg@ARM.comvoid 25913641Sqtt2@cornell.eduDefaultRename<Impl>::clearStates(ThreadID tid) 26013641Sqtt2@cornell.edu{ 26113641Sqtt2@cornell.edu renameStatus[tid] = Idle; 26213641Sqtt2@cornell.edu 26313641Sqtt2@cornell.edu freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 26413641Sqtt2@cornell.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 26513641Sqtt2@cornell.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 26613641Sqtt2@cornell.edu freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 26713641Sqtt2@cornell.edu emptyROB[tid] = true; 26813641Sqtt2@cornell.edu 26913641Sqtt2@cornell.edu stalls[tid].iew = false; 27013641Sqtt2@cornell.edu serializeInst[tid] = NULL; 27113641Sqtt2@cornell.edu 27213641Sqtt2@cornell.edu instsInProgress[tid] = 0; 27313641Sqtt2@cornell.edu loadsInProgress[tid] = 0; 27413641Sqtt2@cornell.edu storesInProgress[tid] = 0; 27513641Sqtt2@cornell.edu 27613641Sqtt2@cornell.edu serializeOnNextInst[tid] = false; 27713641Sqtt2@cornell.edu} 27813641Sqtt2@cornell.edu 27913641Sqtt2@cornell.edutemplate <class Impl> 28013641Sqtt2@cornell.eduvoid 2819444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2829444SAndreas.Sandberg@ARM.com{ 2839444SAndreas.Sandberg@ARM.com _status = Inactive; 2849444SAndreas.Sandberg@ARM.com 2859444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2869444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2879444SAndreas.Sandberg@ARM.com 2882329SN/A // Grab the number of free entries directly from the stages. 2896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2909444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2919444SAndreas.Sandberg@ARM.com 2922292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 29310239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 29410239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 2952292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2962292SN/A emptyROB[tid] = true; 2979444SAndreas.Sandberg@ARM.com 2989444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2999444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 3009444SAndreas.Sandberg@ARM.com 3019444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 30210239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] = 0; 30310239Sbinhpham@cs.rutgers.edu storesInProgress[tid] = 0; 3049444SAndreas.Sandberg@ARM.com 3059444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 3062292SN/A } 3071060SN/A} 3081060SN/A 3092292SN/Atemplate<class Impl> 3102292SN/Avoid 3116221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3122292SN/A{ 3132292SN/A activeThreads = at_ptr; 3142292SN/A} 3152292SN/A 3162292SN/A 3171061SN/Atemplate <class Impl> 3181060SN/Avoid 3192292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 3201060SN/A{ 3216221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3226221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3231060SN/A} 3241060SN/A 3251061SN/Atemplate <class Impl> 3261060SN/Avoid 3272292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 3281060SN/A{ 3292292SN/A freeList = fl_ptr; 3302292SN/A} 3311060SN/A 3322292SN/Atemplate<class Impl> 3332292SN/Avoid 3342292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 3352292SN/A{ 3362292SN/A scoreboard = _scoreboard; 3371060SN/A} 3381060SN/A 3391061SN/Atemplate <class Impl> 3402863Sktlim@umich.edubool 3419444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 3421060SN/A{ 3439444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3449444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 3459444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 3469444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 34711650Srekai.gonzalezalberquilla@arm.com !insts[tid].empty() || 34811650Srekai.gonzalezalberquilla@arm.com (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 3499444SAndreas.Sandberg@ARM.com return false; 3509444SAndreas.Sandberg@ARM.com } 3512863Sktlim@umich.edu return true; 3522316SN/A} 3531060SN/A 3542316SN/Atemplate <class Impl> 3552316SN/Avoid 3562307SN/ADefaultRename<Impl>::takeOverFrom() 3571060SN/A{ 3589444SAndreas.Sandberg@ARM.com resetStage(); 3599444SAndreas.Sandberg@ARM.com} 3601060SN/A 3619444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3629444SAndreas.Sandberg@ARM.comvoid 3639444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3649444SAndreas.Sandberg@ARM.com{ 3656221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3669444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3679444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3689444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3699444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3702307SN/A } 3712307SN/A} 3722307SN/A 3732307SN/Atemplate <class Impl> 3742307SN/Avoid 3756221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3761858SN/A{ 37713831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] [squash sn:%llu] Squashing instructions.\n", 37813831SAndrea.Mondelli@ucf.edu tid,squash_seq_num); 3791858SN/A 3802292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3812292SN/A // If it still needs to block, the blocking should happen the next 3822292SN/A // cycle and there should be space to hold everything due to the squash. 3832292SN/A if (renameStatus[tid] == Blocked || 3843788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3852292SN/A toDecode->renameUnblock[tid] = 1; 3862698Sktlim@umich.edu 3873788Sgblack@eecs.umich.edu resumeSerialize = false; 3882301SN/A serializeInst[tid] = NULL; 3893788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3903788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 39113831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] [squash sn:%llu] " 39213831SAndrea.Mondelli@ucf.edu "Rename will resume serializing after squash\n", 39313831SAndrea.Mondelli@ucf.edu tid,squash_seq_num); 3943788Sgblack@eecs.umich.edu resumeSerialize = true; 3953788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3963788Sgblack@eecs.umich.edu } else { 3973788Sgblack@eecs.umich.edu resumeSerialize = false; 3983788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3993788Sgblack@eecs.umich.edu 4003788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 4013788Sgblack@eecs.umich.edu } 4022292SN/A } 4032292SN/A 4042292SN/A // Set the status to Squashing. 4052292SN/A renameStatus[tid] = Squashing; 4062292SN/A 4072329SN/A // Squash any instructions from decode. 4082292SN/A for (int i=0; i<fromDecode->size; i++) { 4092935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 4102935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 4112731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 4122292SN/A wroteToTimeBuffer = true; 4132292SN/A } 4142935Sksewell@umich.edu 4152292SN/A } 4162292SN/A 4172935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 4184632Sgblack@eecs.umich.edu // insts in them. 4193093Sksewell@umich.edu insts[tid].clear(); 4202292SN/A 4212292SN/A // Clear the skid buffer in case it has any data in it. 4223093Sksewell@umich.edu skidBuffer[tid].clear(); 4234632Sgblack@eecs.umich.edu 4242935Sksewell@umich.edu doSquash(squash_seq_num, tid); 4252292SN/A} 4262292SN/A 4272292SN/Atemplate <class Impl> 4282292SN/Avoid 4292292SN/ADefaultRename<Impl>::tick() 4302292SN/A{ 4312292SN/A wroteToTimeBuffer = false; 4322292SN/A 4332292SN/A blockThisCycle = false; 4342292SN/A 4352292SN/A bool status_change = false; 4362292SN/A 4372292SN/A toIEWIndex = 0; 4382292SN/A 4392292SN/A sortInsts(); 4402292SN/A 4416221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4426221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4432292SN/A 4442292SN/A // Check stall and squash signals. 4453867Sbinkertn@umich.edu while (threads != end) { 4466221Snate@binkert.org ThreadID tid = *threads++; 4472292SN/A 4482292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4492292SN/A 4502292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4512292SN/A 4522292SN/A rename(status_change, tid); 4532292SN/A } 4542292SN/A 4552292SN/A if (status_change) { 4562292SN/A updateStatus(); 4572292SN/A } 4582292SN/A 4592292SN/A if (wroteToTimeBuffer) { 4602292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4612292SN/A cpu->activityThisCycle(); 4622292SN/A } 4632292SN/A 4643867Sbinkertn@umich.edu threads = activeThreads->begin(); 4652292SN/A 4663867Sbinkertn@umich.edu while (threads != end) { 4676221Snate@binkert.org ThreadID tid = *threads++; 4682292SN/A 4692292SN/A // If we committed this cycle then doneSeqNum will be > 0 4702292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4712292SN/A !fromCommit->commitInfo[tid].squash && 4722292SN/A renameStatus[tid] != Squashing) { 4732292SN/A 4742292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4752292SN/A tid); 4762292SN/A } 4772292SN/A } 4782292SN/A 4792292SN/A // @todo: make into updateProgress function 4806221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4812292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 48210239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 48310239Sbinhpham@cs.rutgers.edu storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 48410239Sbinhpham@cs.rutgers.edu assert(loadsInProgress[tid] >= 0); 48510239Sbinhpham@cs.rutgers.edu assert(storesInProgress[tid] >= 0); 4862292SN/A assert(instsInProgress[tid] >=0); 4872292SN/A } 4882292SN/A 4892292SN/A} 4902292SN/A 4912292SN/Atemplate<class Impl> 4922292SN/Avoid 4936221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4942292SN/A{ 4952292SN/A // If status is Running or idle, 4962292SN/A // call renameInsts() 4972292SN/A // If status is Unblocking, 4982292SN/A // buffer any instructions coming from decode 4992292SN/A // continue trying to empty skid buffer 5002292SN/A // check if stall conditions have passed 5012292SN/A 5022292SN/A if (renameStatus[tid] == Blocked) { 5032292SN/A ++renameBlockCycles; 5042292SN/A } else if (renameStatus[tid] == Squashing) { 5052292SN/A ++renameSquashCycles; 5062301SN/A } else if (renameStatus[tid] == SerializeStall) { 5072301SN/A ++renameSerializeStallCycles; 5083788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 5093788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 5103788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 5113788Sgblack@eecs.umich.edu if (resumeSerialize) { 5123788Sgblack@eecs.umich.edu resumeSerialize = false; 5133788Sgblack@eecs.umich.edu block(tid); 5143788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 5153788Sgblack@eecs.umich.edu } 5163798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 5173798Sgblack@eecs.umich.edu if (resumeUnblocking) { 5183798Sgblack@eecs.umich.edu block(tid); 5193798Sgblack@eecs.umich.edu resumeUnblocking = false; 5203798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 5213798Sgblack@eecs.umich.edu } 5222292SN/A } 5232292SN/A 5242292SN/A if (renameStatus[tid] == Running || 5252292SN/A renameStatus[tid] == Idle) { 52613831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 52713831SAndrea.Mondelli@ucf.edu "[tid:%i] " 52813831SAndrea.Mondelli@ucf.edu "Not blocked, so attempting to run stage.\n", 52913831SAndrea.Mondelli@ucf.edu tid); 5302292SN/A 5312292SN/A renameInsts(tid); 5322292SN/A } else if (renameStatus[tid] == Unblocking) { 5332292SN/A renameInsts(tid); 5342292SN/A 5352292SN/A if (validInsts()) { 5362292SN/A // Add the current inputs to the skid buffer so they can be 5372292SN/A // reprocessed when this stage unblocks. 5382292SN/A skidInsert(tid); 5392292SN/A } 5402292SN/A 5412292SN/A // If we switched over to blocking, then there's a potential for 5422292SN/A // an overall status change. 5432292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5441858SN/A } 5451858SN/A} 5461858SN/A 5471858SN/Atemplate <class Impl> 5481858SN/Avoid 5496221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5501858SN/A{ 5512292SN/A // Instructions can be either in the skid buffer or the queue of 5522292SN/A // instructions coming from decode, depending on the status. 5532292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5542292SN/A skidBuffer[tid].size() : insts[tid].size(); 5551858SN/A 5562292SN/A // Check the decode queue to see if instructions are available. 5572292SN/A // If there are no available instructions to rename, then do nothing. 5582292SN/A if (insts_available == 0) { 55913831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Nothing to do, breaking out early.\n", 5602292SN/A tid); 5612292SN/A // Should I change status to idle? 5622292SN/A ++renameIdleCycles; 5632292SN/A return; 5642292SN/A } else if (renameStatus[tid] == Unblocking) { 5652292SN/A ++renameUnblockCycles; 5662292SN/A } else if (renameStatus[tid] == Running) { 5672292SN/A ++renameRunCycles; 5682292SN/A } 5691858SN/A 5702292SN/A // Will have to do a different calculation for the number of free 5712292SN/A // entries. 5722292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5732292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5742292SN/A int min_free_entries = free_rob_entries; 5752292SN/A 5762292SN/A FullSource source = ROB; 5772292SN/A 5782292SN/A if (free_iq_entries < min_free_entries) { 5792292SN/A min_free_entries = free_iq_entries; 5802292SN/A source = IQ; 5812292SN/A } 5822292SN/A 5832292SN/A // Check if there's any space left. 5842292SN/A if (min_free_entries <= 0) { 58513831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 58613831SAndrea.Mondelli@ucf.edu "[tid:%i] Blocking due to no free ROB/IQ/ entries.\n" 5872292SN/A "ROB has %i free entries.\n" 58810239Sbinhpham@cs.rutgers.edu "IQ has %i free entries.\n", 58913831SAndrea.Mondelli@ucf.edu tid, free_rob_entries, free_iq_entries); 5902292SN/A 5912292SN/A blockThisCycle = true; 5922292SN/A 5932292SN/A block(tid); 5942292SN/A 5952292SN/A incrFullStat(source); 5962292SN/A 5972292SN/A return; 5982292SN/A } else if (min_free_entries < insts_available) { 59913831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 60013831SAndrea.Mondelli@ucf.edu "[tid:%i] " 60113831SAndrea.Mondelli@ucf.edu "Will have to block this cycle. " 60213831SAndrea.Mondelli@ucf.edu "%i insts available, " 60313831SAndrea.Mondelli@ucf.edu "but only %i insts can be renamed due to ROB/IQ/LSQ limits.\n", 6042292SN/A tid, insts_available, min_free_entries); 6052292SN/A 6062292SN/A insts_available = min_free_entries; 6072292SN/A 6082292SN/A blockThisCycle = true; 6092292SN/A 6102292SN/A incrFullStat(source); 6112292SN/A } 6122292SN/A 6132292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 6142292SN/A skidBuffer[tid] : insts[tid]; 6152292SN/A 61613831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 61713831SAndrea.Mondelli@ucf.edu "[tid:%i] " 61813831SAndrea.Mondelli@ucf.edu "%i available instructions to send iew.\n", 61913831SAndrea.Mondelli@ucf.edu tid, insts_available); 6202292SN/A 62113831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 62213831SAndrea.Mondelli@ucf.edu "[tid:%i] " 62313831SAndrea.Mondelli@ucf.edu "%i insts pipelining from Rename | " 62413831SAndrea.Mondelli@ucf.edu "%i insts dispatched to IQ last cycle.\n", 6252292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 6262292SN/A 6272292SN/A // Handle serializing the next instruction if necessary. 6282292SN/A if (serializeOnNextInst[tid]) { 6292292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 6302292SN/A // ROB already empty; no need to serialize. 6312292SN/A serializeOnNextInst[tid] = false; 6322292SN/A } else if (!insts_to_rename.empty()) { 6332292SN/A insts_to_rename.front()->setSerializeBefore(); 6342292SN/A } 6352292SN/A } 6362292SN/A 6372292SN/A int renamed_insts = 0; 6382292SN/A 6392292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 64013831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Sending instructions to IEW.\n", tid); 6412292SN/A 6422292SN/A assert(!insts_to_rename.empty()); 6432292SN/A 64413429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = insts_to_rename.front(); 6452292SN/A 64610239Sbinhpham@cs.rutgers.edu //For all kind of instructions, check ROB and IQ first 64710239Sbinhpham@cs.rutgers.edu //For load instruction, check LQ size and take into account the inflight loads 64810239Sbinhpham@cs.rutgers.edu //For store instruction, check SQ size and take into account the inflight stores 64910239Sbinhpham@cs.rutgers.edu 65010239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 65110933Snilay@cs.wisc.edu if (calcFreeLQEntries(tid) <= 0) { 65213831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Cannot rename due to no free LQ\n"); 65310933Snilay@cs.wisc.edu source = LQ; 65410933Snilay@cs.wisc.edu incrFullStat(source); 65510933Snilay@cs.wisc.edu break; 65610933Snilay@cs.wisc.edu } 65710239Sbinhpham@cs.rutgers.edu } 65810239Sbinhpham@cs.rutgers.edu 65913652Sqtt2@cornell.edu if (inst->isStore() || inst->isAtomic()) { 66010933Snilay@cs.wisc.edu if (calcFreeSQEntries(tid) <= 0) { 66113831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Cannot rename due to no free SQ\n"); 66210933Snilay@cs.wisc.edu source = SQ; 66310933Snilay@cs.wisc.edu incrFullStat(source); 66410933Snilay@cs.wisc.edu break; 66510933Snilay@cs.wisc.edu } 66610239Sbinhpham@cs.rutgers.edu } 66710239Sbinhpham@cs.rutgers.edu 6682292SN/A insts_to_rename.pop_front(); 6692292SN/A 6702292SN/A if (renameStatus[tid] == Unblocking) { 67113831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 67213831SAndrea.Mondelli@ucf.edu "[tid:%i] " 67313831SAndrea.Mondelli@ucf.edu "Removing [sn:%llu] PC:%s from rename skidBuffer\n", 67413831SAndrea.Mondelli@ucf.edu tid, inst->seqNum, inst->pcState()); 6752292SN/A } 6762292SN/A 6772292SN/A if (inst->isSquashed()) { 67813831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 67913831SAndrea.Mondelli@ucf.edu "[tid:%i] " 68013831SAndrea.Mondelli@ucf.edu "instruction %i with PC %s is squashed, skipping.\n", 68113831SAndrea.Mondelli@ucf.edu tid, inst->seqNum, inst->pcState()); 6822292SN/A 6832292SN/A ++renameSquashedInsts; 6842292SN/A 6852292SN/A // Decrement how many instructions are available. 6862292SN/A --insts_available; 6872292SN/A 6882292SN/A continue; 6892292SN/A } 6902292SN/A 69113831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 69213831SAndrea.Mondelli@ucf.edu "[tid:%i] " 69313831SAndrea.Mondelli@ucf.edu "Processing instruction [sn:%llu] with PC %s.\n", 69413831SAndrea.Mondelli@ucf.edu tid, inst->seqNum, inst->pcState()); 6952292SN/A 6969531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6979531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 69810715SRekai.GonzalezAlberquilla@arm.com if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 69910715SRekai.GonzalezAlberquilla@arm.com inst->numFPDestRegs(), 70012109SRekai.GonzalezAlberquilla@arm.com inst->numVecDestRegs(), 70112109SRekai.GonzalezAlberquilla@arm.com inst->numVecElemDestRegs(), 70213610Sgiacomo.gabrielli@arm.com inst->numVecPredDestRegs(), 70310935Snilay@cs.wisc.edu inst->numCCDestRegs())) { 70413831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 70513831SAndrea.Mondelli@ucf.edu "Blocking due to " 70613831SAndrea.Mondelli@ucf.edu " lack of free physical registers to rename to.\n"); 7079531Sgeoffrey.blake@arm.com blockThisCycle = true; 7089531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 7099531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 7109531Sgeoffrey.blake@arm.com 7119531Sgeoffrey.blake@arm.com break; 7129531Sgeoffrey.blake@arm.com } 7139531Sgeoffrey.blake@arm.com 7142292SN/A // Handle serializeAfter/serializeBefore instructions. 7152292SN/A // serializeAfter marks the next instruction as serializeBefore. 7162292SN/A // serializeBefore makes the instruction wait in rename until the ROB 7172292SN/A // is empty. 7182336SN/A 7192336SN/A // In this model, IPR accesses are serialize before 7202336SN/A // instructions, and store conditionals are serialize after 7212336SN/A // instructions. This is mainly due to lack of support for 7222336SN/A // out-of-order operations of either of those classes of 7232336SN/A // instructions. 7242336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 7252336SN/A !inst->isSerializeHandled()) { 7262292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 7272292SN/A 7282301SN/A if (!inst->isTempSerializeBefore()) { 7292301SN/A renamedSerializing++; 7302292SN/A inst->setSerializeHandled(); 7312301SN/A } else { 7322301SN/A renamedTempSerializing++; 7332301SN/A } 7342292SN/A 7352301SN/A // Change status over to SerializeStall so that other stages know 7362292SN/A // what this is blocked on. 7372301SN/A renameStatus[tid] = SerializeStall; 7382292SN/A 7392301SN/A serializeInst[tid] = inst; 7402292SN/A 7412292SN/A blockThisCycle = true; 7422292SN/A 7432292SN/A break; 7442336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 7452336SN/A !inst->isSerializeHandled()) { 7462292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 7472292SN/A 7482307SN/A renamedSerializing++; 7492307SN/A 7502292SN/A inst->setSerializeHandled(); 7512292SN/A 7522292SN/A serializeAfter(insts_to_rename, tid); 7532292SN/A } 7542292SN/A 7552292SN/A renameSrcRegs(inst, inst->threadNumber); 7562292SN/A 7572292SN/A renameDestRegs(inst, inst->threadNumber); 7582292SN/A 75913652Sqtt2@cornell.edu if (inst->isAtomic() || inst->isStore()) { 76013652Sqtt2@cornell.edu storesInProgress[tid]++; 76113652Sqtt2@cornell.edu } else if (inst->isLoad()) { 76213652Sqtt2@cornell.edu loadsInProgress[tid]++; 76310239Sbinhpham@cs.rutgers.edu } 76413652Sqtt2@cornell.edu 7652292SN/A ++renamed_insts; 76611246Sradhika.jagtap@ARM.com // Notify potential listeners that source and destination registers for 76711246Sradhika.jagtap@ARM.com // this instruction have been renamed. 76811246Sradhika.jagtap@ARM.com ppRename->notify(inst); 7698471SGiacomo.Gabrielli@arm.com 7702292SN/A // Put instruction in rename queue. 7712292SN/A toIEW->insts[toIEWIndex] = inst; 7722292SN/A ++(toIEW->size); 7732292SN/A 7742292SN/A // Increment which instruction we're on. 7752292SN/A ++toIEWIndex; 7762292SN/A 7772292SN/A // Decrement how many instructions are available. 7782292SN/A --insts_available; 7792292SN/A } 7802292SN/A 7812292SN/A instsInProgress[tid] += renamed_insts; 7822307SN/A renameRenamedInsts += renamed_insts; 7832292SN/A 7842292SN/A // If we wrote to the time buffer, record this. 7852292SN/A if (toIEWIndex) { 7862292SN/A wroteToTimeBuffer = true; 7872292SN/A } 7882292SN/A 7892292SN/A // Check if there's any instructions left that haven't yet been renamed. 7902292SN/A // If so then block. 7912292SN/A if (insts_available) { 7922292SN/A blockThisCycle = true; 7932292SN/A } 7942292SN/A 7952292SN/A if (blockThisCycle) { 7962292SN/A block(tid); 7972292SN/A toDecode->renameUnblock[tid] = false; 7982292SN/A } 7992292SN/A} 8002292SN/A 8012292SN/Atemplate<class Impl> 8022292SN/Avoid 8036221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 8042292SN/A{ 8052292SN/A DynInstPtr inst = NULL; 8062292SN/A 8072292SN/A while (!insts[tid].empty()) { 8082292SN/A inst = insts[tid].front(); 8092292SN/A 8102292SN/A insts[tid].pop_front(); 8112292SN/A 8122292SN/A assert(tid == inst->threadNumber); 8132292SN/A 81413831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Inserting [sn:%llu] PC: %s into Rename " 8157720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 8162292SN/A 8172307SN/A ++renameSkidInsts; 8182307SN/A 8192292SN/A skidBuffer[tid].push_back(inst); 8202292SN/A } 8212292SN/A 8222292SN/A if (skidBuffer[tid].size() > skidBufferMax) 8233798Sgblack@eecs.umich.edu { 8243798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 8253798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 82611321Ssteve.reinhardt@amd.com for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 8273798Sgblack@eecs.umich.edu { 82813831SAndrea.Mondelli@ucf.edu warn("[tid:%i] %s [sn:%llu].\n", tid, 8297720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 8303798Sgblack@eecs.umich.edu (*it)->seqNum); 8313798Sgblack@eecs.umich.edu } 8322292SN/A panic("Skidbuffer Exceeded Max Size"); 8333798Sgblack@eecs.umich.edu } 8342292SN/A} 8352292SN/A 8362292SN/Atemplate <class Impl> 8372292SN/Avoid 8382292SN/ADefaultRename<Impl>::sortInsts() 8392292SN/A{ 8402292SN/A int insts_from_decode = fromDecode->size; 8412292SN/A for (int i = 0; i < insts_from_decode; ++i) { 84213429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst = fromDecode->insts[i]; 8432292SN/A insts[inst->threadNumber].push_back(inst); 8449527SMatt.Horsnell@arm.com#if TRACING_ON 8459527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 8469527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 8479527SMatt.Horsnell@arm.com } 8489527SMatt.Horsnell@arm.com#endif 8492292SN/A } 8502292SN/A} 8512292SN/A 8522292SN/Atemplate<class Impl> 8532292SN/Abool 8542292SN/ADefaultRename<Impl>::skidsEmpty() 8552292SN/A{ 8566221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8576221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8582292SN/A 8593867Sbinkertn@umich.edu while (threads != end) { 8606221Snate@binkert.org ThreadID tid = *threads++; 8613867Sbinkertn@umich.edu 8623867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 8632292SN/A return false; 8642292SN/A } 8652292SN/A 8662292SN/A return true; 8672292SN/A} 8682292SN/A 8692292SN/Atemplate<class Impl> 8702292SN/Avoid 8712292SN/ADefaultRename<Impl>::updateStatus() 8722292SN/A{ 8732292SN/A bool any_unblocking = false; 8742292SN/A 8756221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8766221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8772292SN/A 8783867Sbinkertn@umich.edu while (threads != end) { 8796221Snate@binkert.org ThreadID tid = *threads++; 8802292SN/A 8812292SN/A if (renameStatus[tid] == Unblocking) { 8822292SN/A any_unblocking = true; 8832292SN/A break; 8842292SN/A } 8852292SN/A } 8862292SN/A 8872292SN/A // Rename will have activity if it's unblocking. 8882292SN/A if (any_unblocking) { 8892292SN/A if (_status == Inactive) { 8902292SN/A _status = Active; 8912292SN/A 8922292SN/A DPRINTF(Activity, "Activating stage.\n"); 8932292SN/A 8942733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8952292SN/A } 8962292SN/A } else { 8972292SN/A // If it's not unblocking, then rename will not have any internal 8982292SN/A // activity. Switch it to inactive. 8992292SN/A if (_status == Active) { 9002292SN/A _status = Inactive; 9012292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9022292SN/A 9032733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 9042292SN/A } 9052292SN/A } 9062292SN/A} 9072292SN/A 9082292SN/Atemplate <class Impl> 9092292SN/Abool 9106221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 9112292SN/A{ 91213831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Blocking.\n", tid); 9132292SN/A 9142292SN/A // Add the current inputs onto the skid buffer, so they can be 9152292SN/A // reprocessed when this stage unblocks. 9162292SN/A skidInsert(tid); 9172292SN/A 9182292SN/A // Only signal backwards to block if the previous stages do not think 9192292SN/A // rename is already blocked. 9202292SN/A if (renameStatus[tid] != Blocked) { 9213798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 9223798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 9233798Sgblack@eecs.umich.edu // stages to block. 9243798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 9252292SN/A toDecode->renameBlock[tid] = true; 9262292SN/A toDecode->renameUnblock[tid] = false; 9272292SN/A wroteToTimeBuffer = true; 9282292SN/A } 9292292SN/A 9302329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 9312329SN/A // it would not know to complete the serialize stall. 9322301SN/A if (renameStatus[tid] != SerializeStall) { 9332292SN/A // Set status to Blocked. 9342292SN/A renameStatus[tid] = Blocked; 9352292SN/A return true; 9362292SN/A } 9372292SN/A } 9382292SN/A 9392292SN/A return false; 9402292SN/A} 9412292SN/A 9422292SN/Atemplate <class Impl> 9432292SN/Abool 9446221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 9452292SN/A{ 94613831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Trying to unblock.\n", tid); 9472292SN/A 9482292SN/A // Rename is done unblocking if the skid buffer is empty. 9492301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 9502292SN/A 95113831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Done unblocking.\n", tid); 9522292SN/A 9532292SN/A toDecode->renameUnblock[tid] = true; 9542292SN/A wroteToTimeBuffer = true; 9552292SN/A 9562292SN/A renameStatus[tid] = Running; 9572292SN/A return true; 9582292SN/A } 9592292SN/A 9602292SN/A return false; 9612292SN/A} 9622292SN/A 9632292SN/Atemplate <class Impl> 9642292SN/Avoid 9656221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 9662292SN/A{ 9672980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9682980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 9692292SN/A 9701060SN/A // After a syscall squashes everything, the history buffer may be empty 9711060SN/A // but the ROB may still be squashing instructions. 9721060SN/A // Go through the most recent instructions, undoing the mappings 9731060SN/A // they did and freeing up the registers. 9742292SN/A while (!historyBuffer[tid].empty() && 9759919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 9762292SN/A assert(hb_it != historyBuffer[tid].end()); 9771062SN/A 97813831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Removing history entry with sequence " 97914025Sgiacomo.gabrielli@arm.com "number %i (archReg: %d, newPhysReg: %d, prevPhysReg: %d).\n", 98014025Sgiacomo.gabrielli@arm.com tid, hb_it->instSeqNum, hb_it->archReg.index(), 98114025Sgiacomo.gabrielli@arm.com hb_it->newPhysReg->index(), hb_it->prevPhysReg->index()); 9821060SN/A 9839919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 9849919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 9859919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 9869919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 9879919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 9889919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 9899919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9909919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 9919919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 9929919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9931060SN/A 9949919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 9959919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 9969919Ssteve.reinhardt@amd.com } 9971062SN/A 99811246Sradhika.jagtap@ARM.com // Notify potential listeners that the register mapping needs to be 99911246Sradhika.jagtap@ARM.com // removed because the instruction it was mapped to got squashed. Note 100011246Sradhika.jagtap@ARM.com // that this is done before hb_it is incremented. 100111246Sradhika.jagtap@ARM.com ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 100211246Sradhika.jagtap@ARM.com hb_it->newPhysReg)); 100311246Sradhika.jagtap@ARM.com 10042292SN/A historyBuffer[tid].erase(hb_it++); 10051061SN/A 10061062SN/A ++renameUndoneMaps; 10071060SN/A } 100813601Sgiacomo.travaglini@arm.com 100913601Sgiacomo.travaglini@arm.com // Check if we need to change vector renaming mode after squashing 101013601Sgiacomo.travaglini@arm.com cpu->switchRenameMode(tid, freeList); 10111060SN/A} 10121060SN/A 10131060SN/Atemplate<class Impl> 10141060SN/Avoid 10156221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 10161060SN/A{ 101713831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Removing a committed instruction from the " 101813831SAndrea.Mondelli@ucf.edu "history buffer %u (size=%i), until [sn:%llu].\n", 10192292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 10202292SN/A 10212980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 10222980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 10231060SN/A 10241061SN/A --hb_it; 10251060SN/A 10262292SN/A if (historyBuffer[tid].empty()) { 102713831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] History buffer is empty.\n", tid); 10282292SN/A return; 10292292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 103013831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] [sn:%llu] " 103113831SAndrea.Mondelli@ucf.edu "Old sequence number encountered. " 103213831SAndrea.Mondelli@ucf.edu "Ensure that a syscall happened recently.\n", 103313831SAndrea.Mondelli@ucf.edu tid,inst_seq_num); 10341060SN/A return; 10351060SN/A } 10361060SN/A 10372292SN/A // Commit all the renames up until (and including) the committed sequence 10382292SN/A // number. Some or even all of the committed instructions may not have 10392292SN/A // rename histories if they did not have destination registers that were 10402292SN/A // renamed. 10412292SN/A while (!historyBuffer[tid].empty() && 10422292SN/A hb_it != historyBuffer[tid].end() && 10439919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 10441060SN/A 104513831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Freeing up older rename of reg %i (%s), " 104613831SAndrea.Mondelli@ucf.edu "[sn:%llu].\n", 104712106SRekai.GonzalezAlberquilla@arm.com tid, hb_it->prevPhysReg->index(), 104812106SRekai.GonzalezAlberquilla@arm.com hb_it->prevPhysReg->className(), 104912105Snathanael.premillieu@arm.com hb_it->instSeqNum); 10501061SN/A 10519919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 10529919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 10539919Ssteve.reinhardt@amd.com // the old one. 10549919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 10559919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 10569919Ssteve.reinhardt@amd.com } 10579919Ssteve.reinhardt@amd.com 10582292SN/A ++renameCommittedMaps; 10591061SN/A 10602292SN/A historyBuffer[tid].erase(hb_it--); 10611060SN/A } 10621060SN/A} 10631060SN/A 10641061SN/Atemplate <class Impl> 10651061SN/Ainline void 106613429Srekai.gonzalezalberquilla@arm.comDefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid) 10671061SN/A{ 10689919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10699919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10701061SN/A unsigned num_src_regs = inst->numSrcRegs(); 10711061SN/A 10721061SN/A // Get the architectual register numbers from the source and 10739919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 10742292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 107512106SRekai.GonzalezAlberquilla@arm.com const RegId& src_reg = inst->srcRegIdx(src_idx); 107612105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_reg; 10779919Ssteve.reinhardt@amd.com 107812106SRekai.GonzalezAlberquilla@arm.com renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 107912106SRekai.GonzalezAlberquilla@arm.com switch (src_reg.classValue()) { 10809913Ssteve.reinhardt@amd.com case IntRegClass: 10819919Ssteve.reinhardt@amd.com intRenameLookups++; 10829913Ssteve.reinhardt@amd.com break; 10839913Ssteve.reinhardt@amd.com case FloatRegClass: 10849919Ssteve.reinhardt@amd.com fpRenameLookups++; 10859913Ssteve.reinhardt@amd.com break; 108612144Srekai.gonzalezalberquilla@arm.com case VecRegClass: 108713598Sgiacomo.travaglini@arm.com case VecElemClass: 108812144Srekai.gonzalezalberquilla@arm.com vecRenameLookups++; 108912144Srekai.gonzalezalberquilla@arm.com break; 109013610Sgiacomo.gabrielli@arm.com case VecPredRegClass: 109113610Sgiacomo.gabrielli@arm.com vecPredRenameLookups++; 109213610Sgiacomo.gabrielli@arm.com break; 10939920Syasuko.eckert@amd.com case CCRegClass: 10949913Ssteve.reinhardt@amd.com case MiscRegClass: 10959913Ssteve.reinhardt@amd.com break; 10969913Ssteve.reinhardt@amd.com 10979913Ssteve.reinhardt@amd.com default: 109812106SRekai.GonzalezAlberquilla@arm.com panic("Invalid register class: %d.", src_reg.classValue()); 10993773Sgblack@eecs.umich.edu } 11004352Sgblack@eecs.umich.edu 110113831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 110213831SAndrea.Mondelli@ucf.edu "[tid:%i] " 110313831SAndrea.Mondelli@ucf.edu "Looking up %s arch reg %i, got phys reg %i (%s)\n", 110413831SAndrea.Mondelli@ucf.edu tid, src_reg.className(), 110513831SAndrea.Mondelli@ucf.edu src_reg.index(), renamed_reg->index(), 110612106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 11071061SN/A 11081061SN/A inst->renameSrcReg(src_idx, renamed_reg); 11091061SN/A 11102292SN/A // See if the register is ready or not. 11119919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 111213831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 111313831SAndrea.Mondelli@ucf.edu "[tid:%i] " 111413831SAndrea.Mondelli@ucf.edu "Register %d (flat: %d) (%s) is ready.\n", 111513831SAndrea.Mondelli@ucf.edu tid, renamed_reg->index(), renamed_reg->flatIndex(), 111612106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 11171061SN/A 11181061SN/A inst->markSrcRegReady(src_idx); 11194636Sgblack@eecs.umich.edu } else { 112013831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 112113831SAndrea.Mondelli@ucf.edu "[tid:%i] " 112213831SAndrea.Mondelli@ucf.edu "Register %d (flat: %d) (%s) is not ready.\n", 112313831SAndrea.Mondelli@ucf.edu tid, renamed_reg->index(), renamed_reg->flatIndex(), 112412106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 11251061SN/A } 11261062SN/A 11271062SN/A ++renameRenameLookups; 11281061SN/A } 11291061SN/A} 11301061SN/A 11311061SN/Atemplate <class Impl> 11321061SN/Ainline void 113313429Srekai.gonzalezalberquilla@arm.comDefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid) 11341061SN/A{ 11359919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 11369919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 11371061SN/A unsigned num_dest_regs = inst->numDestRegs(); 11381061SN/A 11392292SN/A // Rename the destination registers. 11402292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 114112106SRekai.GonzalezAlberquilla@arm.com const RegId& dest_reg = inst->destRegIdx(dest_idx); 11429919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 11439919Ssteve.reinhardt@amd.com 114412106SRekai.GonzalezAlberquilla@arm.com RegId flat_dest_regid = tc->flattenRegId(dest_reg); 114514025Sgiacomo.gabrielli@arm.com flat_dest_regid.setNumPinnedWrites(dest_reg.getNumPinnedWrites()); 11469913Ssteve.reinhardt@amd.com 114712106SRekai.GonzalezAlberquilla@arm.com rename_result = map->rename(flat_dest_regid); 11489913Ssteve.reinhardt@amd.com 114912106SRekai.GonzalezAlberquilla@arm.com inst->flattenDestReg(dest_idx, flat_dest_regid); 11501061SN/A 11519916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 11521062SN/A 115313831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 115413831SAndrea.Mondelli@ucf.edu "[tid:%i] " 115513831SAndrea.Mondelli@ucf.edu "Renaming arch reg %i (%s) to physical reg %i (%i).\n", 115613831SAndrea.Mondelli@ucf.edu tid, dest_reg.index(), dest_reg.className(), 115712106SRekai.GonzalezAlberquilla@arm.com rename_result.first->index(), 115812106SRekai.GonzalezAlberquilla@arm.com rename_result.first->flatIndex()); 11591062SN/A 11602292SN/A // Record the rename information so that a history can be kept. 116112106SRekai.GonzalezAlberquilla@arm.com RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 11622292SN/A rename_result.first, 11632292SN/A rename_result.second); 11641062SN/A 11652292SN/A historyBuffer[tid].push_front(hb_entry); 11661062SN/A 116713831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] [sn:%llu] " 116813831SAndrea.Mondelli@ucf.edu "Adding instruction to history buffer (size=%i).\n", 116913831SAndrea.Mondelli@ucf.edu tid,(*historyBuffer[tid].begin()).instSeqNum, 117013831SAndrea.Mondelli@ucf.edu historyBuffer[tid].size()); 11711062SN/A 11722292SN/A // Tell the instruction to rename the appropriate destination 11732292SN/A // register (dest_idx) to the new physical register 11742292SN/A // (rename_result.first), and record the previous physical 11752292SN/A // register that the same logical register was renamed to 11762292SN/A // (rename_result.second). 11772292SN/A inst->renameDestReg(dest_idx, 11782292SN/A rename_result.first, 11792292SN/A rename_result.second); 11801062SN/A 11812292SN/A ++renameRenamedOperands; 11821061SN/A } 11831061SN/A} 11841061SN/A 11851061SN/Atemplate <class Impl> 11861061SN/Ainline int 11876221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11881061SN/A{ 11892292SN/A int num_free = freeEntries[tid].robEntries - 11902292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11912292SN/A 119213831SAndrea.Mondelli@ucf.edu //DPRINTF(Rename,"[tid:%i] %i rob free\n",tid,num_free); 11932292SN/A 11942292SN/A return num_free; 11951061SN/A} 11961061SN/A 11971061SN/Atemplate <class Impl> 11981061SN/Ainline int 11996221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 12001061SN/A{ 12012292SN/A int num_free = freeEntries[tid].iqEntries - 12022292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 12032292SN/A 120413831SAndrea.Mondelli@ucf.edu //DPRINTF(Rename,"[tid:%i] %i iq free\n",tid,num_free); 12052292SN/A 12062292SN/A return num_free; 12072292SN/A} 12082292SN/A 12092292SN/Atemplate <class Impl> 12102292SN/Ainline int 121110239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 12122292SN/A{ 121310239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].lqEntries - 121410935Snilay@cs.wisc.edu (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 121513831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 121613831SAndrea.Mondelli@ucf.edu "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 121713831SAndrea.Mondelli@ucf.edu "loads dispatchedToLQ: %d\n", 121813831SAndrea.Mondelli@ucf.edu freeEntries[tid].lqEntries, loadsInProgress[tid], 121913831SAndrea.Mondelli@ucf.edu fromIEW->iewInfo[tid].dispatchedToLQ); 122010239Sbinhpham@cs.rutgers.edu return num_free; 122110239Sbinhpham@cs.rutgers.edu} 12222292SN/A 122310239Sbinhpham@cs.rutgers.edutemplate <class Impl> 122410239Sbinhpham@cs.rutgers.eduinline int 122510239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 122610239Sbinhpham@cs.rutgers.edu{ 122710239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].sqEntries - 122810935Snilay@cs.wisc.edu (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 122910239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 123010239Sbinhpham@cs.rutgers.edu "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 123110239Sbinhpham@cs.rutgers.edu storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 123210239Sbinhpham@cs.rutgers.edu return num_free; 12332292SN/A} 12342292SN/A 12352292SN/Atemplate <class Impl> 12362292SN/Aunsigned 12372292SN/ADefaultRename<Impl>::validInsts() 12382292SN/A{ 12392292SN/A unsigned inst_count = 0; 12402292SN/A 12412292SN/A for (int i=0; i<fromDecode->size; i++) { 12422731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 12432292SN/A inst_count++; 12442292SN/A } 12452292SN/A 12462292SN/A return inst_count; 12472292SN/A} 12482292SN/A 12492292SN/Atemplate <class Impl> 12502292SN/Avoid 12516221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 12522292SN/A{ 12532292SN/A if (fromIEW->iewBlock[tid]) { 12542292SN/A stalls[tid].iew = true; 12552292SN/A } 12562292SN/A 12572292SN/A if (fromIEW->iewUnblock[tid]) { 12582292SN/A assert(stalls[tid].iew); 12592292SN/A stalls[tid].iew = false; 12602292SN/A } 12612292SN/A} 12622292SN/A 12632292SN/Atemplate <class Impl> 12642292SN/Abool 12656221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 12662292SN/A{ 12672292SN/A bool ret_val = false; 12682292SN/A 12692292SN/A if (stalls[tid].iew) { 127013831SAndrea.Mondelli@ucf.edu DPRINTF(Rename,"[tid:%i] Stall from IEW stage detected.\n", tid); 12712292SN/A ret_val = true; 12722292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 127313831SAndrea.Mondelli@ucf.edu DPRINTF(Rename,"[tid:%i] Stall: ROB has 0 free entries.\n", tid); 12742292SN/A ret_val = true; 12752292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 127613831SAndrea.Mondelli@ucf.edu DPRINTF(Rename,"[tid:%i] Stall: IQ has 0 free entries.\n", tid); 12772292SN/A ret_val = true; 127810239Sbinhpham@cs.rutgers.edu } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 127913831SAndrea.Mondelli@ucf.edu DPRINTF(Rename,"[tid:%i] Stall: LSQ has 0 free entries.\n", tid); 12802292SN/A ret_val = true; 12812292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 128213831SAndrea.Mondelli@ucf.edu DPRINTF(Rename,"[tid:%i] Stall: RenameMap has 0 free entries.\n", tid); 12832292SN/A ret_val = true; 12842301SN/A } else if (renameStatus[tid] == SerializeStall && 12852292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 128613831SAndrea.Mondelli@ucf.edu DPRINTF(Rename,"[tid:%i] Stall: Serialize stall and ROB is not " 12872292SN/A "empty.\n", 12882292SN/A tid); 12892292SN/A ret_val = true; 12902292SN/A } 12912292SN/A 12922292SN/A return ret_val; 12932292SN/A} 12942292SN/A 12952292SN/Atemplate <class Impl> 12962292SN/Avoid 12976221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12982292SN/A{ 12998607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 13008607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 13012292SN/A 130210239Sbinhpham@cs.rutgers.edu if (fromIEW->iewInfo[tid].usedLSQ) { 130310239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 130410239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 130510239Sbinhpham@cs.rutgers.edu } 13062292SN/A 13072292SN/A if (fromCommit->commitInfo[tid].usedROB) { 13082292SN/A freeEntries[tid].robEntries = 13092292SN/A fromCommit->commitInfo[tid].freeROBEntries; 13102292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 13112292SN/A } 13122292SN/A 131313831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Free IQ: %i, Free ROB: %i, " 131413610Sgiacomo.gabrielli@arm.com "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n", 13152292SN/A tid, 13162292SN/A freeEntries[tid].iqEntries, 13172292SN/A freeEntries[tid].robEntries, 131810239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries, 131912109SRekai.GonzalezAlberquilla@arm.com freeEntries[tid].sqEntries, 132012109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeEntries(), 132112109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeIntEntries(), 132212109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeFloatEntries(), 132312109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeVecEntries(), 132413610Sgiacomo.gabrielli@arm.com renameMap[tid]->numFreePredEntries(), 132512109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeCCEntries()); 13262292SN/A 132713831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] %i instructions not yet in ROB\n", 13282292SN/A tid, instsInProgress[tid]); 13292292SN/A} 13302292SN/A 13312292SN/Atemplate <class Impl> 13322292SN/Abool 13336221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 13342292SN/A{ 13352292SN/A // Check if there's a squash signal, squash if there is 13362292SN/A // Check stall signals, block if necessary. 13372292SN/A // If status was blocked 13382292SN/A // check if stall conditions have passed 13392292SN/A // if so then go to unblocking 13402292SN/A // If status was Squashing 13412292SN/A // check if squashing is not high. Switch to running this cycle. 13422301SN/A // If status was serialize stall 13432292SN/A // check if ROB is empty and no insts are in flight to the ROB 13442292SN/A 13452292SN/A readFreeEntries(tid); 13462292SN/A readStallSignals(tid); 13472292SN/A 13482292SN/A if (fromCommit->commitInfo[tid].squash) { 134913831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Squashing instructions due to squash from " 13502292SN/A "commit.\n", tid); 13512292SN/A 13524632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 13532292SN/A 13542292SN/A return true; 13552292SN/A } 13562292SN/A 13572292SN/A if (checkStall(tid)) { 13582292SN/A return block(tid); 13592292SN/A } 13602292SN/A 13612292SN/A if (renameStatus[tid] == Blocked) { 136213831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Done blocking, switching to unblocking.\n", 13632292SN/A tid); 13642292SN/A 13652292SN/A renameStatus[tid] = Unblocking; 13662292SN/A 13672292SN/A unblock(tid); 13682292SN/A 13692292SN/A return true; 13702292SN/A } 13712292SN/A 13722292SN/A if (renameStatus[tid] == Squashing) { 13732292SN/A // Switch status to running if rename isn't being told to block or 13742292SN/A // squash this cycle. 13753798Sgblack@eecs.umich.edu if (resumeSerialize) { 137613831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 137713831SAndrea.Mondelli@ucf.edu "[tid:%i] Done squashing, switching to serialize.\n", tid); 13782292SN/A 13793798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 13803798Sgblack@eecs.umich.edu return true; 13813798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 138213831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, 138313831SAndrea.Mondelli@ucf.edu "[tid:%i] Done squashing, switching to unblocking.\n", 13843798Sgblack@eecs.umich.edu tid); 13853798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13863798Sgblack@eecs.umich.edu return true; 13873798Sgblack@eecs.umich.edu } else { 138813831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Done squashing, switching to running.\n", 13893788Sgblack@eecs.umich.edu tid); 13903788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13913788Sgblack@eecs.umich.edu return false; 13923788Sgblack@eecs.umich.edu } 13932292SN/A } 13942292SN/A 13952301SN/A if (renameStatus[tid] == SerializeStall) { 13962292SN/A // Stall ends once the ROB is free. 139713831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Done with serialize stall, switching to " 13982292SN/A "unblocking.\n", tid); 13992292SN/A 14002301SN/A DynInstPtr serial_inst = serializeInst[tid]; 14012292SN/A 14022292SN/A renameStatus[tid] = Unblocking; 14032292SN/A 14042292SN/A unblock(tid); 14052292SN/A 140613831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Processing instruction [%lli] with " 14077720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 14082292SN/A 14092292SN/A // Put instruction into queue here. 14102301SN/A serial_inst->clearSerializeBefore(); 14112292SN/A 14122292SN/A if (!skidBuffer[tid].empty()) { 14132301SN/A skidBuffer[tid].push_front(serial_inst); 14142292SN/A } else { 14152301SN/A insts[tid].push_front(serial_inst); 14162292SN/A } 14172292SN/A 141813831SAndrea.Mondelli@ucf.edu DPRINTF(Rename, "[tid:%i] Instruction must be processed by rename." 14192703Sktlim@umich.edu " Adding to front of list.\n", tid); 14202292SN/A 14212301SN/A serializeInst[tid] = NULL; 14222292SN/A 14232292SN/A return true; 14242292SN/A } 14252292SN/A 14262292SN/A // If we've reached this point, we have not gotten any signals that 14272292SN/A // cause rename to change its status. Rename remains the same as before. 14282292SN/A return false; 14291061SN/A} 14301061SN/A 14311060SN/Atemplate<class Impl> 14321060SN/Avoid 14336221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 14341060SN/A{ 14352292SN/A if (inst_list.empty()) { 14362292SN/A // Mark a bit to say that I must serialize on the next instruction. 14372292SN/A serializeOnNextInst[tid] = true; 14381060SN/A return; 14391060SN/A } 14401060SN/A 14412292SN/A // Set the next instruction as serializing. 14422292SN/A inst_list.front()->setSerializeBefore(); 14432292SN/A} 14442292SN/A 14452292SN/Atemplate <class Impl> 14462292SN/Ainline void 14472292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 14482292SN/A{ 14492292SN/A switch (source) { 14502292SN/A case ROB: 14512292SN/A ++renameROBFullEvents; 14522292SN/A break; 14532292SN/A case IQ: 14542292SN/A ++renameIQFullEvents; 14552292SN/A break; 145610239Sbinhpham@cs.rutgers.edu case LQ: 145710239Sbinhpham@cs.rutgers.edu ++renameLQFullEvents; 145810239Sbinhpham@cs.rutgers.edu break; 145910239Sbinhpham@cs.rutgers.edu case SQ: 146010239Sbinhpham@cs.rutgers.edu ++renameSQFullEvents; 14612292SN/A break; 14622292SN/A default: 14632292SN/A panic("Rename full stall stat should be incremented for a reason!"); 14642292SN/A break; 14651060SN/A } 14662292SN/A} 14671060SN/A 14682292SN/Atemplate <class Impl> 14692292SN/Avoid 14702292SN/ADefaultRename<Impl>::dumpHistory() 14712292SN/A{ 14722980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 14731060SN/A 14746221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 14751060SN/A 14766221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 14771060SN/A 14786221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 147912105Snathanael.premillieu@arm.com cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 148012105Snathanael.premillieu@arm.com " %i[%s] Old phys reg: %i[%s]\n", 148112105Snathanael.premillieu@arm.com (*buf_it).instSeqNum, 148212106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.className(), 148312106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.index(), 148412106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->index(), 148512106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->className(), 148612106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->index(), 148712106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->className()); 14881060SN/A 14892292SN/A buf_it++; 14901062SN/A } 14911060SN/A } 14921060SN/A} 14939944Smatt.horsnell@ARM.com 14949944Smatt.horsnell@ARM.com#endif//__CPU_O3_RENAME_IMPL_HH__ 1495