18012Ssaidi@eecs.umich.edu/* 28029Snate@binkert.org * Copyright (c) 2003-2004 The Regents of The University of Michigan 38029Snate@binkert.org * Copyright (c) 1993 The Hewlett-Packard Development Company 48029Snate@binkert.org * All rights reserved. 58013Sbinkertn@umich.edu * 68029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 78029Snate@binkert.org * modification, are permitted provided that the following conditions are 88029Snate@binkert.org * met: redistributions of source code must retain the above copyright 98029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 108029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 118029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 128029Snate@binkert.org * documentation and/or other materials provided with the distribution; 138029Snate@binkert.org * neither the name of the copyright holders nor the names of its 148029Snate@binkert.org * contributors may be used to endorse or promote products derived from 158029Snate@binkert.org * this software without specific prior written permission. 168013Sbinkertn@umich.edu * 178029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 188029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 198029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 208029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 218029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 228029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 238029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 248029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 258029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 268029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 278029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 288013Sbinkertn@umich.edu */ 298012Ssaidi@eecs.umich.edu 308008Ssaidi@eecs.umich.edu/* 318008Ssaidi@eecs.umich.edu * Debug Monitor Entry code 328008Ssaidi@eecs.umich.edu */ 338008Ssaidi@eecs.umich.edu#include "fromHudsonOsf.h" 348008Ssaidi@eecs.umich.edu 358023Ssaidi@eecs.umich.edu .extern myAlphaAccess 368008Ssaidi@eecs.umich.edu .text 378008Ssaidi@eecs.umich.edu 388008Ssaidi@eecs.umich.edu/* return address and padding to octaword align */ 398008Ssaidi@eecs.umich.edu#define STARTFRM 16 408008Ssaidi@eecs.umich.edu 418013Sbinkertn@umich.edu .globl _start 428013Sbinkertn@umich.edu .ent _start, 0 438013Sbinkertn@umich.edu_start: 448008Ssaidi@eecs.umich.edu_entry: 458008Ssaidi@eecs.umich.edu br t0, 2f # get the current PC 468008Ssaidi@eecs.umich.edu2: ldgp gp, 0(t0) # init gp 478008Ssaidi@eecs.umich.edu 488023Ssaidi@eecs.umich.edu/* Processor 0 start stack frame is begining of physical memory (0) 498023Ssaidi@eecs.umich.edu Other processors spin here waiting to get their stacks from 508023Ssaidi@eecs.umich.edu Processor 0, then they can progress as normal. 518023Ssaidi@eecs.umich.edu*/ 528023Ssaidi@eecs.umich.edu call_pal PAL_WHAMI_ENTRY 538023Ssaidi@eecs.umich.edu beq v0, cpuz 548023Ssaidi@eecs.umich.edu ldq t3, m5AlphaAccess 558023Ssaidi@eecs.umich.edu addq t3,0x70,t3 # *** If offset in console alpha access struct changes 568023Ssaidi@eecs.umich.edu # This must be changed as well! 578023Ssaidi@eecs.umich.edu bis zero,8,t4 588023Ssaidi@eecs.umich.edu mulq t4,v0,t4 598023Ssaidi@eecs.umich.edu addq t3,t4,t3 608024Ssaidi@eecs.umich.edu ldah a0, 3(zero) # load arg0 with 65536*3 618024Ssaidi@eecs.umich.educpuwait: .long 0x6000002 # jsr quiesceNs 628024Ssaidi@eecs.umich.edu ldq t4, 0(t3) 638023Ssaidi@eecs.umich.edu beq t4, cpuwait 648023Ssaidi@eecs.umich.edu bis t4,t4,sp 658008Ssaidi@eecs.umich.edu 668023Ssaidi@eecs.umich.edu 678023Ssaidi@eecs.umich.educpuz: bis sp,sp,s0 /* save sp */ 688008Ssaidi@eecs.umich.edu 698008Ssaidi@eecs.umich.eduslave: lda v0,(8*1024)(sp) /* end of page */ 708008Ssaidi@eecs.umich.edu 718008Ssaidi@eecs.umich.edu subq zero, 1, t0 728008Ssaidi@eecs.umich.edu sll t0, 42, t0 738008Ssaidi@eecs.umich.edu bis t0, v0, sp 748008Ssaidi@eecs.umich.edu 758008Ssaidi@eecs.umich.edu lda sp, -STARTFRM(sp) # Create a stack frame 768008Ssaidi@eecs.umich.edu stq ra, 0(sp) # Place return address on the stack 778008Ssaidi@eecs.umich.edu 788008Ssaidi@eecs.umich.edu .mask 0x84000000, -8 798008Ssaidi@eecs.umich.edu .frame sp, STARTFRM, ra 808008Ssaidi@eecs.umich.edu 818008Ssaidi@eecs.umich.edu/* 828008Ssaidi@eecs.umich.edu * Enable the Floating Point Unit 838008Ssaidi@eecs.umich.edu */ 848008Ssaidi@eecs.umich.edu lda a0, 1(zero) 858008Ssaidi@eecs.umich.edu call_pal PAL_WRFEN_ENTRY 868008Ssaidi@eecs.umich.edu 878008Ssaidi@eecs.umich.edu/* 888008Ssaidi@eecs.umich.edu * Every good C program has a main() 898008Ssaidi@eecs.umich.edu */ 908008Ssaidi@eecs.umich.edu 918023Ssaidi@eecs.umich.edu/* If stack pointer was 0, then this is CPU0*/ 928008Ssaidi@eecs.umich.edu beq s0,master 938008Ssaidi@eecs.umich.edu 948008Ssaidi@eecs.umich.edu call_pal PAL_WHAMI_ENTRY 958008Ssaidi@eecs.umich.edu bis v0,v0,a0 968008Ssaidi@eecs.umich.edu jsr ra, SlaveLoop 978008Ssaidi@eecs.umich.edumaster: 988008Ssaidi@eecs.umich.edu jsr ra, main 998008Ssaidi@eecs.umich.edu 1008008Ssaidi@eecs.umich.edu 1018008Ssaidi@eecs.umich.edu 1028008Ssaidi@eecs.umich.edu/* 1038008Ssaidi@eecs.umich.edu * The Debug Monitor should never return. 1048008Ssaidi@eecs.umich.edu * However, just incase... 1058008Ssaidi@eecs.umich.edu */ 1068008Ssaidi@eecs.umich.edu ldgp gp, 0(ra) 1078008Ssaidi@eecs.umich.edu bsr zero, _exit 1088008Ssaidi@eecs.umich.edu 1098013Sbinkertn@umich.edu.end _start 1108008Ssaidi@eecs.umich.edu 1118008Ssaidi@eecs.umich.edu 1128008Ssaidi@eecs.umich.edu 1138008Ssaidi@eecs.umich.edu .globl _exit 1148008Ssaidi@eecs.umich.edu .ent _exit, 0 1158008Ssaidi@eecs.umich.edu_exit: 1168008Ssaidi@eecs.umich.edu 1178008Ssaidi@eecs.umich.edu ldq ra, 0(sp) # restore return address 1188008Ssaidi@eecs.umich.edu lda sp, STARTFRM(sp) # prune back the stack 1198008Ssaidi@eecs.umich.edu ret zero, (ra) # Back from whence we came 1208008Ssaidi@eecs.umich.edu.end _exit 1218008Ssaidi@eecs.umich.edu 1228008Ssaidi@eecs.umich.edu .globl cServe 1238008Ssaidi@eecs.umich.edu .ent cServe 2 1248008Ssaidi@eecs.umich.educServe: 1258008Ssaidi@eecs.umich.edu .option O1 1268008Ssaidi@eecs.umich.edu .frame sp, 0, ra 1278008Ssaidi@eecs.umich.edu call_pal PAL_CSERVE_ENTRY 1288008Ssaidi@eecs.umich.edu ret zero, (ra) 1298008Ssaidi@eecs.umich.edu .end cServe 1308008Ssaidi@eecs.umich.edu 1318008Ssaidi@eecs.umich.edu .globl wrfen 1328008Ssaidi@eecs.umich.edu .ent wrfen 2 1338008Ssaidi@eecs.umich.eduwrfen: 1348008Ssaidi@eecs.umich.edu .option O1 1358008Ssaidi@eecs.umich.edu .frame sp, 0, ra 1368008Ssaidi@eecs.umich.edu call_pal PAL_WRFEN_ENTRY 1378008Ssaidi@eecs.umich.edu ret zero, (ra) 1388008Ssaidi@eecs.umich.edu .end wrfen 1398008Ssaidi@eecs.umich.edu .globl consoleCallback 1408008Ssaidi@eecs.umich.edu .ent consoleCallback 2 1418008Ssaidi@eecs.umich.educonsoleCallback: 1428008Ssaidi@eecs.umich.edu br t0, 2f # get the current PC 1438008Ssaidi@eecs.umich.edu2: ldgp gp, 0(t0) # init gp 1448008Ssaidi@eecs.umich.edu lda sp,-64(sp) 1458008Ssaidi@eecs.umich.edu stq ra,0(sp) 1468008Ssaidi@eecs.umich.edu jsr CallBackDispatcher 1478008Ssaidi@eecs.umich.edu ldq ra,0(sp) 1488008Ssaidi@eecs.umich.edu lda sp,64(sp) 1498008Ssaidi@eecs.umich.edu ret zero,(ra) 1508008Ssaidi@eecs.umich.edu .end consoleCallback 1518008Ssaidi@eecs.umich.edu 1528008Ssaidi@eecs.umich.edu 1538008Ssaidi@eecs.umich.edu .globl consoleFixup 1548008Ssaidi@eecs.umich.edu .ent consoleFixup 2 1558008Ssaidi@eecs.umich.educonsoleFixup: 1568008Ssaidi@eecs.umich.edu br t0, 2f # get the current PC 1578008Ssaidi@eecs.umich.edu2: ldgp gp, 0(t0) # init gp 1588008Ssaidi@eecs.umich.edu lda sp,-64(sp) 1598008Ssaidi@eecs.umich.edu stq ra,0(sp) 1608008Ssaidi@eecs.umich.edu jsr CallBackFixup 1618008Ssaidi@eecs.umich.edu ldq ra,0(sp) 1628008Ssaidi@eecs.umich.edu lda sp,64(sp) 1638008Ssaidi@eecs.umich.edu ret zero,(ra) 1648008Ssaidi@eecs.umich.edu .end consoleFixup 1658008Ssaidi@eecs.umich.edu 1668008Ssaidi@eecs.umich.edu 1678008Ssaidi@eecs.umich.edu 1688008Ssaidi@eecs.umich.edu .globl SpinLock 1698008Ssaidi@eecs.umich.edu .ent SpinLock 2 1708008Ssaidi@eecs.umich.eduSpinLock: 1718008Ssaidi@eecs.umich.edu1: 1728008Ssaidi@eecs.umich.edu ldq_l a1,0(a0) # interlock complete lock state 1738008Ssaidi@eecs.umich.edu subl ra,3,v0 # get calling addr[31:0] + 1 1748008Ssaidi@eecs.umich.edu blbs a1,2f # branch if lock is busy 1758008Ssaidi@eecs.umich.edu stq_c v0,0(a0) # attempt to acquire lock 1768008Ssaidi@eecs.umich.edu beq v0,2f # branch if lost atomicity 1778008Ssaidi@eecs.umich.edu mb # ensure memory coherence 1788008Ssaidi@eecs.umich.edu ret zero,(ra) # return to caller (v0 is 1) 1798008Ssaidi@eecs.umich.edu2: 1808008Ssaidi@eecs.umich.edu br zero,1b 1818008Ssaidi@eecs.umich.edu .end SpinLock 1828008Ssaidi@eecs.umich.edu 1838008Ssaidi@eecs.umich.edu .globl loadContext 1848008Ssaidi@eecs.umich.edu .ent loadContext 2 1858008Ssaidi@eecs.umich.eduloadContext: 1868008Ssaidi@eecs.umich.edu .option O1 1878008Ssaidi@eecs.umich.edu .frame sp, 0, ra 1888008Ssaidi@eecs.umich.edu call_pal PAL_SWPCTX_ENTRY 1898008Ssaidi@eecs.umich.edu ret zero, (ra) 1908008Ssaidi@eecs.umich.edu .end loadContext 1918008Ssaidi@eecs.umich.edu 1928008Ssaidi@eecs.umich.edu 1938008Ssaidi@eecs.umich.edu .globl SlaveSpin # Very carefully spin wait 1948008Ssaidi@eecs.umich.edu .ent SlaveSpin 2 # and swap context without 1958008Ssaidi@eecs.umich.eduSlaveSpin: # using any stack space 1968008Ssaidi@eecs.umich.edu .option O1 1978008Ssaidi@eecs.umich.edu .frame sp, 0, ra 1988008Ssaidi@eecs.umich.edu mov a0, t0 # cpu number 1998008Ssaidi@eecs.umich.edu mov a1, t1 # cpu rpb pointer (virtual) 2008008Ssaidi@eecs.umich.edu mov a2, t2 # what to spin on 2018024Ssaidi@eecs.umich.edu ldah a0, 3(zero) # load arg0 with 65536 2028024Ssaidi@eecs.umich.edutest: .long 0x6000002 # jsr quiesceNs # wait 65us*3 2038024Ssaidi@eecs.umich.edu ldl t3, 0(t2) 2048008Ssaidi@eecs.umich.edu beq t3, test 2058008Ssaidi@eecs.umich.edu zapnot t1,0x1f,a0 # make rpb physical 2068008Ssaidi@eecs.umich.edu call_pal PAL_SWPCTX_ENTRY # switch to pcb 2078008Ssaidi@eecs.umich.edu mov t0, a0 # setup args for SlaveCmd 2088008Ssaidi@eecs.umich.edu mov t1, a1 2098008Ssaidi@eecs.umich.edu jsr SlaveCmd # call SlaveCmd 2108008Ssaidi@eecs.umich.edu ret zero, (ra) # Should never be reached 2118008Ssaidi@eecs.umich.edu .end SlaveSpin 2128008Ssaidi@eecs.umich.edu 2138008Ssaidi@eecs.umich.edu 214