1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * Copyright (c) 1993 The Hewlett-Packard Development Company
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * Debug Monitor Entry code
32 */
33#include "fromHudsonOsf.h"
34
35        .extern myAlphaAccess
36        .text
37
38/* return address and padding to octaword align */
39#define STARTFRM 16
40
41        .globl  _start
42        .ent    _start, 0
43_start:
44_entry:
45        br      t0, 2f			# get the current PC
462:	ldgp    gp, 0(t0)               # init gp
47
48/* Processor 0 start stack frame is begining of physical memory (0)
49   Other processors spin here waiting to get their stacks from
50   Processor 0, then they can progress as normal.
51*/
52        call_pal PAL_WHAMI_ENTRY
53        beq v0, cpuz
54        ldq  t3, m5AlphaAccess
55        addq t3,0x70,t3 # *** If offset in console alpha access struct changes
56                        # This must be changed as well!
57        bis  zero,8,t4
58        mulq t4,v0,t4
59        addq t3,t4,t3
60        ldah a0, 3(zero)  # load arg0 with 65536*3
61cpuwait: .long 0x6000002  # jsr quiesceNs
62        ldq  t4, 0(t3)
63        beq  t4, cpuwait
64        bis  t4,t4,sp
65
66
67cpuz:	bis	sp,sp,s0 /* save sp */
68
69slave:	lda	v0,(8*1024)(sp) /* end of page  */
70
71        subq	zero, 1, t0
72        sll	t0, 42, t0
73        bis	t0, v0, sp
74
75        lda     sp, -STARTFRM(sp)	# Create a stack frame
76        stq     ra, 0(sp)		# Place return address on the stack
77
78        .mask   0x84000000, -8
79        .frame  sp, STARTFRM, ra
80
81/*
82 *	Enable the Floating Point Unit
83 */
84        lda	a0, 1(zero)
85        call_pal PAL_WRFEN_ENTRY
86
87/*
88 *	Every good C program has a main()
89 */
90
91/* If stack pointer was 0, then this is CPU0*/
92        beq	s0,master
93
94        call_pal PAL_WHAMI_ENTRY
95        bis	v0,v0,a0
96        jsr	ra, SlaveLoop
97master:
98        jsr	ra, main
99
100
101
102/*
103 *	The Debug Monitor should never return.
104 *	However, just incase...
105 */
106        ldgp	gp, 0(ra)
107        bsr	zero, _exit
108
109.end	_start
110
111
112
113        .globl  _exit
114        .ent    _exit, 0
115_exit:
116
117        ldq     ra, 0(sp)		# restore return address
118        lda	sp, STARTFRM(sp)	# prune back the stack
119        ret	zero, (ra)		# Back from whence we came
120.end	_exit
121
122                .globl	cServe
123        .ent	cServe 2
124cServe:
125        .option	O1
126        .frame	sp, 0, ra
127        call_pal PAL_CSERVE_ENTRY
128        ret	zero, (ra)
129        .end	cServe
130
131        .globl	wrfen
132        .ent	wrfen 2
133wrfen:
134        .option	O1
135        .frame	sp, 0, ra
136        call_pal PAL_WRFEN_ENTRY
137        ret	zero, (ra)
138        .end	wrfen
139        .globl	consoleCallback
140        .ent	consoleCallback 2
141consoleCallback:
142        br      t0, 2f			# get the current PC
1432:	ldgp    gp, 0(t0)               # init gp
144        lda     sp,-64(sp)
145        stq     ra,0(sp)
146        jsr     CallBackDispatcher
147        ldq     ra,0(sp)
148        lda     sp,64(sp)
149        ret     zero,(ra)
150        .end    consoleCallback
151
152
153        .globl	consoleFixup
154        .ent	consoleFixup 2
155consoleFixup:
156        br      t0, 2f			# get the current PC
1572:	ldgp    gp, 0(t0)               # init gp
158        lda     sp,-64(sp)
159        stq     ra,0(sp)
160        jsr     CallBackFixup
161        ldq     ra,0(sp)
162        lda     sp,64(sp)
163        ret     zero,(ra)
164        .end    consoleFixup
165
166
167
168        .globl	SpinLock
169        .ent	SpinLock 2
170SpinLock:
1711:
172        ldq_l	a1,0(a0)		# interlock complete lock state
173        subl	ra,3,v0			# get calling addr[31:0] + 1
174        blbs	a1,2f			# branch if lock is busy
175        stq_c	v0,0(a0)		# attempt to acquire lock
176        beq	v0,2f			# branch if lost atomicity
177        mb				# ensure memory coherence
178        ret	zero,(ra)		# return to caller (v0 is 1)
1792:
180        br	zero,1b
181        .end	SpinLock
182
183        .globl	loadContext
184        .ent	loadContext 2
185loadContext:
186        .option	O1
187        .frame	sp, 0, ra
188        call_pal PAL_SWPCTX_ENTRY
189        ret	zero, (ra)
190        .end	loadContext
191
192
193        .globl	SlaveSpin          # Very carefully spin wait
194        .ent	SlaveSpin 2        # and swap context without
195SlaveSpin:                         # using any stack space
196        .option	O1
197        .frame	sp, 0, ra
198        mov a0, t0                 # cpu number
199        mov a1, t1                 # cpu rpb pointer (virtual)
200        mov a2, t2                 # what to spin on
201        ldah a0, 3(zero)  # load arg0 with 65536
202test:   .long 0x6000002  # jsr quiesceNs     # wait 65us*3
203        ldl  t3, 0(t2)
204        beq  t3, test
205        zapnot t1,0x1f,a0          # make rpb physical
206        call_pal PAL_SWPCTX_ENTRY  # switch to pcb
207        mov t0, a0                 # setup args for SlaveCmd
208        mov t1, a1
209        jsr SlaveCmd               # call SlaveCmd
210        ret	zero, (ra)         # Should never be reached
211        .end	SlaveSpin
212
213
214