111320Ssteve.reinhardt@amd.com/* 210328Smitch.hayenga@arm.com * Copyright (c) 2012, 2014 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_DECODE_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_DECODE_IMPL_HH__ 459944Smatt.horsnell@ARM.com 468230Snate@binkert.org#include "arch/types.hh" 478230Snate@binkert.org#include "base/trace.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 491717SN/A#include "cpu/o3/decode.hh" 508230Snate@binkert.org#include "cpu/inst_seq.hh" 518232Snate@binkert.org#include "debug/Activity.hh" 528232Snate@binkert.org#include "debug/Decode.hh" 539527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 546221Snate@binkert.org#include "params/DerivO3CPU.hh" 558793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 561060SN/A 578737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 588737Skoansin.tan@gmail.com// we open up the entire namespace std 598737Skoansin.tan@gmail.comusing std::list; 605529Snate@binkert.org 611060SN/Atemplate<class Impl> 625529Snate@binkert.orgDefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 634329Sktlim@umich.edu : cpu(_cpu), 644329Sktlim@umich.edu renameToDecodeDelay(params->renameToDecodeDelay), 652292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 662292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 672292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 682292SN/A decodeWidth(params->decodeWidth), 695529Snate@binkert.org numThreads(params->numThreads) 701060SN/A{ 7110172Sdam.sunwoo@arm.com if (decodeWidth > Impl::MaxWidth) 7210172Sdam.sunwoo@arm.com fatal("decodeWidth (%d) is larger than compiled limit (%d),\n" 7310172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7410172Sdam.sunwoo@arm.com decodeWidth, static_cast<int>(Impl::MaxWidth)); 7510172Sdam.sunwoo@arm.com 769444SAndreas.Sandberg@ARM.com // @todo: Make into a parameter 779444SAndreas.Sandberg@ARM.com skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; 7813453Srekai.gonzalezalberquilla@arm.com for (int tid = 0; tid < Impl::MaxThreads; tid++) { 7913453Srekai.gonzalezalberquilla@arm.com stalls[tid] = {false}; 8013453Srekai.gonzalezalberquilla@arm.com decodeStatus[tid] = Idle; 8113453Srekai.gonzalezalberquilla@arm.com bdelayDoneSeqNum[tid] = 0; 8213453Srekai.gonzalezalberquilla@arm.com squashInst[tid] = nullptr; 8313453Srekai.gonzalezalberquilla@arm.com squashAfterDelaySlot[tid] = 0; 8413453Srekai.gonzalezalberquilla@arm.com } 859444SAndreas.Sandberg@ARM.com} 869444SAndreas.Sandberg@ARM.com 879444SAndreas.Sandberg@ARM.comtemplate<class Impl> 889444SAndreas.Sandberg@ARM.comvoid 899444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::startupStage() 909444SAndreas.Sandberg@ARM.com{ 919444SAndreas.Sandberg@ARM.com resetStage(); 929444SAndreas.Sandberg@ARM.com} 939444SAndreas.Sandberg@ARM.com 949444SAndreas.Sandberg@ARM.comtemplate<class Impl> 959444SAndreas.Sandberg@ARM.comvoid 9613641Sqtt2@cornell.eduDefaultDecode<Impl>::clearStates(ThreadID tid) 9713641Sqtt2@cornell.edu{ 9813641Sqtt2@cornell.edu decodeStatus[tid] = Idle; 9913641Sqtt2@cornell.edu stalls[tid].rename = false; 10013641Sqtt2@cornell.edu} 10113641Sqtt2@cornell.edu 10213641Sqtt2@cornell.edutemplate<class Impl> 10313641Sqtt2@cornell.eduvoid 1049444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::resetStage() 1059444SAndreas.Sandberg@ARM.com{ 1062292SN/A _status = Inactive; 1072292SN/A 1082348SN/A // Setup status, make sure stall signals are clear. 1096221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1106221Snate@binkert.org decodeStatus[tid] = Idle; 1112292SN/A 1126221Snate@binkert.org stalls[tid].rename = false; 1132292SN/A } 1142292SN/A} 1152292SN/A 1162292SN/Atemplate <class Impl> 1172292SN/Astd::string 1182292SN/ADefaultDecode<Impl>::name() const 1192292SN/A{ 1202292SN/A return cpu->name() + ".decode"; 1211060SN/A} 1221060SN/A 1231062SN/Atemplate <class Impl> 1241062SN/Avoid 1252292SN/ADefaultDecode<Impl>::regStats() 1261062SN/A{ 1271062SN/A decodeIdleCycles 1288240Snate@binkert.org .name(name() + ".IdleCycles") 1291062SN/A .desc("Number of cycles decode is idle") 1301062SN/A .prereq(decodeIdleCycles); 1311062SN/A decodeBlockedCycles 1328240Snate@binkert.org .name(name() + ".BlockedCycles") 1331062SN/A .desc("Number of cycles decode is blocked") 1341062SN/A .prereq(decodeBlockedCycles); 1352292SN/A decodeRunCycles 1368240Snate@binkert.org .name(name() + ".RunCycles") 1372292SN/A .desc("Number of cycles decode is running") 1382292SN/A .prereq(decodeRunCycles); 1391062SN/A decodeUnblockCycles 1408240Snate@binkert.org .name(name() + ".UnblockCycles") 1411062SN/A .desc("Number of cycles decode is unblocking") 1421062SN/A .prereq(decodeUnblockCycles); 1431062SN/A decodeSquashCycles 1448240Snate@binkert.org .name(name() + ".SquashCycles") 1451062SN/A .desc("Number of cycles decode is squashing") 1461062SN/A .prereq(decodeSquashCycles); 1472307SN/A decodeBranchResolved 1488240Snate@binkert.org .name(name() + ".BranchResolved") 1492307SN/A .desc("Number of times decode resolved a branch") 1502307SN/A .prereq(decodeBranchResolved); 1511062SN/A decodeBranchMispred 1528240Snate@binkert.org .name(name() + ".BranchMispred") 1531062SN/A .desc("Number of times decode detected a branch misprediction") 1541062SN/A .prereq(decodeBranchMispred); 1551062SN/A decodeControlMispred 1568240Snate@binkert.org .name(name() + ".ControlMispred") 1571062SN/A .desc("Number of times decode detected an instruction incorrectly" 1581062SN/A " predicted as a control") 1591062SN/A .prereq(decodeControlMispred); 1601062SN/A decodeDecodedInsts 1618240Snate@binkert.org .name(name() + ".DecodedInsts") 1621062SN/A .desc("Number of instructions handled by decode") 1631062SN/A .prereq(decodeDecodedInsts); 1641062SN/A decodeSquashedInsts 1658240Snate@binkert.org .name(name() + ".SquashedInsts") 1661062SN/A .desc("Number of squashed instructions handled by decode") 1671062SN/A .prereq(decodeSquashedInsts); 1681062SN/A} 1691062SN/A 1701060SN/Atemplate<class Impl> 1711060SN/Avoid 1722292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1731060SN/A{ 1741060SN/A timeBuffer = tb_ptr; 1751060SN/A 1761060SN/A // Setup wire to write information back to fetch. 1771060SN/A toFetch = timeBuffer->getWire(0); 1781060SN/A 1791060SN/A // Create wires to get information from proper places in time buffer. 1801060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1811060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1821060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1831060SN/A} 1841060SN/A 1851060SN/Atemplate<class Impl> 1861060SN/Avoid 1872292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1881060SN/A{ 1891060SN/A decodeQueue = dq_ptr; 1901060SN/A 1911060SN/A // Setup wire to write information to proper place in decode queue. 1921060SN/A toRename = decodeQueue->getWire(0); 1931060SN/A} 1941060SN/A 1951060SN/Atemplate<class Impl> 1961060SN/Avoid 1972292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1981060SN/A{ 1991060SN/A fetchQueue = fq_ptr; 2001060SN/A 2011060SN/A // Setup wire to read information from fetch queue. 2021060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 2031060SN/A} 2041060SN/A 2051060SN/Atemplate<class Impl> 2062292SN/Avoid 2076221Snate@binkert.orgDefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 2082292SN/A{ 2092292SN/A activeThreads = at_ptr; 2102292SN/A} 2112292SN/A 2122307SN/Atemplate <class Impl> 2139444SAndreas.Sandberg@ARM.comvoid 2149444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::drainSanityCheck() const 2152307SN/A{ 2166221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2179444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 2189444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 2192307SN/A } 2202307SN/A} 2212307SN/A 22210328Smitch.hayenga@arm.comtemplate <class Impl> 22310328Smitch.hayenga@arm.combool 22410328Smitch.hayenga@arm.comDefaultDecode<Impl>::isDrained() const 22510328Smitch.hayenga@arm.com{ 22610328Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 22711650Srekai.gonzalezalberquilla@arm.com if (!insts[tid].empty() || !skidBuffer[tid].empty() || 22811650Srekai.gonzalezalberquilla@arm.com (decodeStatus[tid] != Running && decodeStatus[tid] != Idle)) 22910328Smitch.hayenga@arm.com return false; 23010328Smitch.hayenga@arm.com } 23110328Smitch.hayenga@arm.com return true; 23210328Smitch.hayenga@arm.com} 23310328Smitch.hayenga@arm.com 2342292SN/Atemplate<class Impl> 2352292SN/Abool 2366221Snate@binkert.orgDefaultDecode<Impl>::checkStall(ThreadID tid) const 2372292SN/A{ 2382292SN/A bool ret_val = false; 2392292SN/A 2402292SN/A if (stalls[tid].rename) { 24113831SAndrea.Mondelli@ucf.edu DPRINTF(Decode,"[tid:%i] Stall fom Rename stage detected.\n", tid); 2422292SN/A ret_val = true; 2432292SN/A } 2442292SN/A 2452292SN/A return ret_val; 2462292SN/A} 2472292SN/A 2482292SN/Atemplate<class Impl> 2491681SN/Ainline bool 2502292SN/ADefaultDecode<Impl>::fetchInstsValid() 2511681SN/A{ 2521681SN/A return fromFetch->size > 0; 2531681SN/A} 2541681SN/A 2551681SN/Atemplate<class Impl> 2562292SN/Abool 2576221Snate@binkert.orgDefaultDecode<Impl>::block(ThreadID tid) 2581060SN/A{ 25913831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Blocking.\n", tid); 2601060SN/A 2611060SN/A // Add the current inputs to the skid buffer so they can be 2621060SN/A // reprocessed when this stage unblocks. 2632292SN/A skidInsert(tid); 2641060SN/A 2652348SN/A // If the decode status is blocked or unblocking then decode has not yet 2662348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2672348SN/A // fetch to block. 2682292SN/A if (decodeStatus[tid] != Blocked) { 2692292SN/A // Set the status to Blocked. 2702292SN/A decodeStatus[tid] = Blocked; 2712348SN/A 2729514SAli.Saidi@ARM.com if (toFetch->decodeUnblock[tid]) { 2739514SAli.Saidi@ARM.com toFetch->decodeUnblock[tid] = false; 2749514SAli.Saidi@ARM.com } else { 2752348SN/A toFetch->decodeBlock[tid] = true; 2762348SN/A wroteToTimeBuffer = true; 2772348SN/A } 2782348SN/A 2792292SN/A return true; 2802292SN/A } 2812292SN/A 2822292SN/A return false; 2831060SN/A} 2841060SN/A 2851060SN/Atemplate<class Impl> 2862292SN/Abool 2876221Snate@binkert.orgDefaultDecode<Impl>::unblock(ThreadID tid) 2881060SN/A{ 2892292SN/A // Decode is done unblocking only if the skid buffer is empty. 2902292SN/A if (skidBuffer[tid].empty()) { 29113831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Done unblocking.\n", tid); 2922292SN/A toFetch->decodeUnblock[tid] = true; 2932292SN/A wroteToTimeBuffer = true; 2941060SN/A 2952292SN/A decodeStatus[tid] = Running; 2962292SN/A return true; 2971060SN/A } 2981681SN/A 29913831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Currently unblocking.\n", tid); 3002329SN/A 3012292SN/A return false; 3021060SN/A} 3031060SN/A 3041060SN/Atemplate<class Impl> 3051060SN/Avoid 30613429Srekai.gonzalezalberquilla@arm.comDefaultDecode<Impl>::squash(const DynInstPtr &inst, ThreadID tid) 3071060SN/A{ 30813831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] [sn:%llu] Squashing due to incorrect branch " 3097720Sgblack@eecs.umich.edu "prediction detected at decode.\n", tid, inst->seqNum); 3102292SN/A 3112348SN/A // Send back mispredict information. 3122292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 3132935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 3148842Smrinmoy.ghosh@arm.com toFetch->decodeInfo[tid].mispredictInst = inst; 3156036Sksewell@umich.edu toFetch->decodeInfo[tid].squash = true; 3162292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 3176036Sksewell@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 3187720Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 3198503Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].squashInst = inst; 3208842Smrinmoy.ghosh@arm.com if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) { 3218842Smrinmoy.ghosh@arm.com toFetch->decodeInfo[tid].branchTaken = true; 3228842Smrinmoy.ghosh@arm.com } 3236036Sksewell@umich.edu 3243093Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 3252935Sksewell@umich.edu 3262348SN/A // Might have to tell fetch to unblock. 3272292SN/A if (decodeStatus[tid] == Blocked || 3282292SN/A decodeStatus[tid] == Unblocking) { 3292292SN/A toFetch->decodeUnblock[tid] = 1; 3302292SN/A } 3312292SN/A 3321060SN/A // Set status to squashing. 3332292SN/A decodeStatus[tid] = Squashing; 3341060SN/A 3352292SN/A for (int i=0; i<fromFetch->size; i++) { 3362292SN/A if (fromFetch->insts[i]->threadNumber == tid && 3372935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 3382731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3392292SN/A } 3402292SN/A } 3412292SN/A 3422348SN/A // Clear the instruction list and skid buffer in case they have any 3432348SN/A // insts in them. 3442292SN/A while (!insts[tid].empty()) { 3452292SN/A insts[tid].pop(); 3462292SN/A } 3471060SN/A 3482292SN/A while (!skidBuffer[tid].empty()) { 3492292SN/A skidBuffer[tid].pop(); 3502292SN/A } 3512292SN/A 3522292SN/A // Squash instructions up until this one 3532935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3542292SN/A} 3552292SN/A 3562292SN/Atemplate<class Impl> 3572292SN/Aunsigned 3586221Snate@binkert.orgDefaultDecode<Impl>::squash(ThreadID tid) 3592292SN/A{ 36013831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Squashing.\n",tid); 3612292SN/A 3622292SN/A if (decodeStatus[tid] == Blocked || 3632292SN/A decodeStatus[tid] == Unblocking) { 3648793Sgblack@eecs.umich.edu if (FullSystem) { 3658793Sgblack@eecs.umich.edu toFetch->decodeUnblock[tid] = 1; 3662292SN/A } else { 3678793Sgblack@eecs.umich.edu // In syscall emulation, we can have both a block and a squash due 3688793Sgblack@eecs.umich.edu // to a syscall in the same cycle. This would cause both signals 3698793Sgblack@eecs.umich.edu // to be high. This shouldn't happen in full system. 3708793Sgblack@eecs.umich.edu // @todo: Determine if this still happens. 3718793Sgblack@eecs.umich.edu if (toFetch->decodeBlock[tid]) 3728793Sgblack@eecs.umich.edu toFetch->decodeBlock[tid] = 0; 3738793Sgblack@eecs.umich.edu else 3748793Sgblack@eecs.umich.edu toFetch->decodeUnblock[tid] = 1; 3752292SN/A } 3762292SN/A } 3772292SN/A 3782292SN/A // Set status to squashing. 3792292SN/A decodeStatus[tid] = Squashing; 3802292SN/A 3812292SN/A // Go through incoming instructions from fetch and squash them. 3822292SN/A unsigned squash_count = 0; 3832292SN/A 3842292SN/A for (int i=0; i<fromFetch->size; i++) { 3852292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3862731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3872292SN/A squash_count++; 3882292SN/A } 3892292SN/A } 3902292SN/A 3912348SN/A // Clear the instruction list and skid buffer in case they have any 3922348SN/A // insts in them. 3932292SN/A while (!insts[tid].empty()) { 3942292SN/A insts[tid].pop(); 3952292SN/A } 3962292SN/A 3972292SN/A while (!skidBuffer[tid].empty()) { 3982292SN/A skidBuffer[tid].pop(); 3992292SN/A } 4002292SN/A 4012292SN/A return squash_count; 4022292SN/A} 4032292SN/A 4042292SN/Atemplate<class Impl> 4052292SN/Avoid 4066221Snate@binkert.orgDefaultDecode<Impl>::skidInsert(ThreadID tid) 4072292SN/A{ 4082292SN/A DynInstPtr inst = NULL; 4092292SN/A 4102292SN/A while (!insts[tid].empty()) { 4112292SN/A inst = insts[tid].front(); 4122292SN/A 4132292SN/A insts[tid].pop(); 4142292SN/A 4152292SN/A assert(tid == inst->threadNumber); 4162292SN/A 41710328Smitch.hayenga@arm.com skidBuffer[tid].push(inst); 4182292SN/A 41910328Smitch.hayenga@arm.com DPRINTF(Decode,"Inserting [tid:%d][sn:%lli] PC: %s into decode skidBuffer %i\n", 42010328Smitch.hayenga@arm.com inst->threadNumber, inst->seqNum, inst->pcState(), skidBuffer[tid].size()); 4212292SN/A } 4222292SN/A 4232329SN/A // @todo: Eventually need to enforce this by not letting a thread 4242292SN/A // fetch past its skidbuffer 4252292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 4262292SN/A} 4272292SN/A 4282292SN/Atemplate<class Impl> 4292292SN/Abool 4302292SN/ADefaultDecode<Impl>::skidsEmpty() 4312292SN/A{ 4326221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4336221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4342292SN/A 4353867Sbinkertn@umich.edu while (threads != end) { 4366221Snate@binkert.org ThreadID tid = *threads++; 4373867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 4382292SN/A return false; 4392292SN/A } 4402292SN/A 4412292SN/A return true; 4422292SN/A} 4432292SN/A 4442292SN/Atemplate<class Impl> 4452292SN/Avoid 4462292SN/ADefaultDecode<Impl>::updateStatus() 4472292SN/A{ 4482292SN/A bool any_unblocking = false; 4492292SN/A 4506221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4516221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4522292SN/A 4533867Sbinkertn@umich.edu while (threads != end) { 4546221Snate@binkert.org ThreadID tid = *threads++; 4552292SN/A 4562292SN/A if (decodeStatus[tid] == Unblocking) { 4572292SN/A any_unblocking = true; 4582292SN/A break; 4592292SN/A } 4602292SN/A } 4612292SN/A 4622292SN/A // Decode will have activity if it's unblocking. 4632292SN/A if (any_unblocking) { 4642292SN/A if (_status == Inactive) { 4652292SN/A _status = Active; 4662292SN/A 4672292SN/A DPRINTF(Activity, "Activating stage.\n"); 4682292SN/A 4692733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4702292SN/A } 4712292SN/A } else { 4722292SN/A // If it's not unblocking, then decode will not have any internal 4732292SN/A // activity. Switch it to inactive. 4742292SN/A if (_status == Active) { 4752292SN/A _status = Inactive; 4762292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4772292SN/A 4782733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4792292SN/A } 4802292SN/A } 4812292SN/A} 4822292SN/A 4832292SN/Atemplate <class Impl> 4842292SN/Avoid 4852292SN/ADefaultDecode<Impl>::sortInsts() 4862292SN/A{ 4872292SN/A int insts_from_fetch = fromFetch->size; 4882292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4892292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4901060SN/A } 4911060SN/A} 4921060SN/A 4931060SN/Atemplate<class Impl> 4941060SN/Avoid 4956221Snate@binkert.orgDefaultDecode<Impl>::readStallSignals(ThreadID tid) 4961060SN/A{ 4972292SN/A if (fromRename->renameBlock[tid]) { 4982292SN/A stalls[tid].rename = true; 4992292SN/A } 5001060SN/A 5012292SN/A if (fromRename->renameUnblock[tid]) { 5022292SN/A assert(stalls[tid].rename); 5032292SN/A stalls[tid].rename = false; 5042292SN/A } 5052292SN/A} 5061060SN/A 5072292SN/Atemplate <class Impl> 5082292SN/Abool 5096221Snate@binkert.orgDefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 5102292SN/A{ 5112292SN/A // Check if there's a squash signal, squash if there is. 5122292SN/A // Check stall signals, block if necessary. 5132292SN/A // If status was blocked 5142292SN/A // Check if stall conditions have passed 5152292SN/A // if so then go to unblocking 5162292SN/A // If status was Squashing 5172292SN/A // check if squashing is not high. Switch to running this cycle. 5181060SN/A 5192292SN/A // Update the per thread stall statuses. 5202292SN/A readStallSignals(tid); 5211060SN/A 5222292SN/A // Check squash signals from commit. 5232292SN/A if (fromCommit->commitInfo[tid].squash) { 5241681SN/A 52513831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Squashing instructions due to squash " 5262292SN/A "from commit.\n", tid); 5272292SN/A 5282292SN/A squash(tid); 5292292SN/A 5302292SN/A return true; 5312292SN/A } 5322292SN/A 5332292SN/A if (checkStall(tid)) { 5342292SN/A return block(tid); 5352292SN/A } 5362292SN/A 5372292SN/A if (decodeStatus[tid] == Blocked) { 53813831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Done blocking, switching to unblocking.\n", 5392292SN/A tid); 5402292SN/A 5412292SN/A decodeStatus[tid] = Unblocking; 5422292SN/A 5432292SN/A unblock(tid); 5442292SN/A 5452292SN/A return true; 5462292SN/A } 5472292SN/A 5482292SN/A if (decodeStatus[tid] == Squashing) { 5492292SN/A // Switch status to running if decode isn't being told to block or 5502292SN/A // squash this cycle. 55113831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Done squashing, switching to running.\n", 5522292SN/A tid); 5532292SN/A 5542292SN/A decodeStatus[tid] = Running; 5552292SN/A 5562292SN/A return false; 5572292SN/A } 5582292SN/A 5592292SN/A // If we've reached this point, we have not gotten any signals that 5602292SN/A // cause decode to change its status. Decode remains the same as before. 5612292SN/A return false; 5622292SN/A} 5632292SN/A 5642292SN/Atemplate<class Impl> 5652292SN/Avoid 5662292SN/ADefaultDecode<Impl>::tick() 5672292SN/A{ 5682292SN/A wroteToTimeBuffer = false; 5692292SN/A 5702292SN/A bool status_change = false; 5712292SN/A 5722292SN/A toRenameIndex = 0; 5732292SN/A 5746221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5756221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5762292SN/A 5772292SN/A sortInsts(); 5782292SN/A 5792292SN/A //Check stall and squash signals. 5803867Sbinkertn@umich.edu while (threads != end) { 5816221Snate@binkert.org ThreadID tid = *threads++; 5822292SN/A 5832292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 5842292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 5852292SN/A 5862292SN/A decode(status_change, tid); 5872292SN/A } 5882292SN/A 5892292SN/A if (status_change) { 5902292SN/A updateStatus(); 5912292SN/A } 5922292SN/A 5932292SN/A if (wroteToTimeBuffer) { 5942292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 5952292SN/A 5962292SN/A cpu->activityThisCycle(); 5971060SN/A } 5981060SN/A} 5991060SN/A 6001060SN/Atemplate<class Impl> 6011060SN/Avoid 6026221Snate@binkert.orgDefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 6031060SN/A{ 6042292SN/A // If status is Running or idle, 6052292SN/A // call decodeInsts() 6062292SN/A // If status is Unblocking, 6072292SN/A // buffer any instructions coming from fetch 6082292SN/A // continue trying to empty skid buffer 6092292SN/A // check if stall conditions have passed 6102292SN/A 6112292SN/A if (decodeStatus[tid] == Blocked) { 6122292SN/A ++decodeBlockedCycles; 6132292SN/A } else if (decodeStatus[tid] == Squashing) { 6142292SN/A ++decodeSquashCycles; 6151060SN/A } 6161060SN/A 6172292SN/A // Decode should try to decode as many instructions as its bandwidth 6182292SN/A // will allow, as long as it is not currently blocked. 6192292SN/A if (decodeStatus[tid] == Running || 6202292SN/A decodeStatus[tid] == Idle) { 62113831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Not blocked, so attempting to run " 6222292SN/A "stage.\n",tid); 6232292SN/A 6242292SN/A decodeInsts(tid); 6252292SN/A } else if (decodeStatus[tid] == Unblocking) { 6262292SN/A // Make sure that the skid buffer has something in it if the 6272292SN/A // status is unblocking. 6282292SN/A assert(!skidsEmpty()); 6292292SN/A 6302292SN/A // If the status was unblocking, then instructions from the skid 6312292SN/A // buffer were used. Remove those instructions and handle 6322292SN/A // the rest of unblocking. 6332292SN/A decodeInsts(tid); 6342292SN/A 6352292SN/A if (fetchInstsValid()) { 6362292SN/A // Add the current inputs to the skid buffer so they can be 6372292SN/A // reprocessed when this stage unblocks. 6382292SN/A skidInsert(tid); 6392292SN/A } 6402292SN/A 6412292SN/A status_change = unblock(tid) || status_change; 6421060SN/A } 6432292SN/A} 6441060SN/A 6452292SN/Atemplate <class Impl> 6462292SN/Avoid 6476221Snate@binkert.orgDefaultDecode<Impl>::decodeInsts(ThreadID tid) 6482292SN/A{ 6492292SN/A // Instructions can come either from the skid buffer or the list of 6502292SN/A // instructions coming from fetch, depending on decode's status. 6512292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6522292SN/A skidBuffer[tid].size() : insts[tid].size(); 6532292SN/A 6542292SN/A if (insts_available == 0) { 65513831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Nothing to do, breaking out" 6562292SN/A " early.\n",tid); 6571060SN/A // Should I change the status to idle? 6581062SN/A ++decodeIdleCycles; 6591060SN/A return; 6602292SN/A } else if (decodeStatus[tid] == Unblocking) { 66113831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Unblocking, removing insts from skid " 6622292SN/A "buffer.\n",tid); 6632292SN/A ++decodeUnblockCycles; 6642292SN/A } else if (decodeStatus[tid] == Running) { 6652292SN/A ++decodeRunCycles; 6661060SN/A } 6671060SN/A 6682292SN/A std::queue<DynInstPtr> 6692292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 6702292SN/A skidBuffer[tid] : insts[tid]; 6711061SN/A 67213831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Sending instruction to rename.\n",tid); 6731060SN/A 6742292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 6752292SN/A assert(!insts_to_decode.empty()); 6761060SN/A 67713429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = std::move(insts_to_decode.front()); 6781062SN/A 6792292SN/A insts_to_decode.pop(); 6801061SN/A 68113831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Processing instruction [sn:%lli] with " 6827720Sgblack@eecs.umich.edu "PC %s\n", tid, inst->seqNum, inst->pcState()); 6831061SN/A 6841061SN/A if (inst->isSquashed()) { 68513831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, "[tid:%i] Instruction %i with PC %s is " 6861061SN/A "squashed, skipping.\n", 6877720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6881061SN/A 6891062SN/A ++decodeSquashedInsts; 6901062SN/A 6911061SN/A --insts_available; 6921061SN/A 6931061SN/A continue; 6941061SN/A } 6951060SN/A 6961681SN/A // Also check if instructions have no source registers. Mark 6971681SN/A // them as ready to issue at any time. Not sure if this check 6981681SN/A // should exist here or at a later stage; however it doesn't matter 6991681SN/A // too much for function correctness. 7001681SN/A if (inst->numSrcRegs() == 0) { 7011681SN/A inst->setCanIssue(); 7021681SN/A } 7031681SN/A 7041060SN/A // This current instruction is valid, so add it into the decode 7051060SN/A // queue. The next instruction may not be valid, so check to 7061060SN/A // see if branches were predicted correctly. 7072292SN/A toRename->insts[toRenameIndex] = inst; 7081061SN/A 7091061SN/A ++(toRename->size); 7102292SN/A ++toRenameIndex; 7112292SN/A ++decodeDecodedInsts; 7122292SN/A --insts_available; 7131060SN/A 7148471SGiacomo.Gabrielli@arm.com#if TRACING_ON 7159527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7169527SMatt.Horsnell@arm.com inst->decodeTick = curTick() - inst->fetchTick; 7179527SMatt.Horsnell@arm.com } 7188471SGiacomo.Gabrielli@arm.com#endif 7198471SGiacomo.Gabrielli@arm.com 7201060SN/A // Ensure that if it was predicted as a branch, it really is a 7211061SN/A // branch. 7223796Sgblack@eecs.umich.edu if (inst->readPredTaken() && !inst->isControl()) { 7231060SN/A panic("Instruction predicted as a branch!"); 7241060SN/A 7251062SN/A ++decodeControlMispred; 7262292SN/A 7271060SN/A // Might want to set some sort of boolean and just do 7281060SN/A // a check at the end 7292292SN/A squash(inst, inst->threadNumber); 7302292SN/A 7311060SN/A break; 7321060SN/A } 7331060SN/A 7341062SN/A // Go ahead and compute any PC-relative branches. 73511781Sarthur.perais@inria.fr // This includes direct unconditional control and 73611781Sarthur.perais@inria.fr // direct conditional control that is predicted taken. 73711781Sarthur.perais@inria.fr if (inst->isDirectCtrl() && 73811781Sarthur.perais@inria.fr (inst->isUncondCtrl() || inst->readPredTaken())) 73911781Sarthur.perais@inria.fr { 7402307SN/A ++decodeBranchResolved; 7411062SN/A 7427720Sgblack@eecs.umich.edu if (!(inst->branchTarget() == inst->readPredTarg())) { 7431062SN/A ++decodeBranchMispred; 7442292SN/A 7451060SN/A // Might want to set some sort of boolean and just do 7461060SN/A // a check at the end 7472292SN/A squash(inst, inst->threadNumber); 7487720Sgblack@eecs.umich.edu TheISA::PCState target = inst->branchTarget(); 7496036Sksewell@umich.edu 75013831SAndrea.Mondelli@ucf.edu DPRINTF(Decode, 75113831SAndrea.Mondelli@ucf.edu "[tid:%i] [sn:%llu] " 75213831SAndrea.Mondelli@ucf.edu "Updating predictions: PredPC: %s\n", 75313831SAndrea.Mondelli@ucf.edu tid, inst->seqNum, target); 7546036Sksewell@umich.edu //The micro pc after an instruction level branch should be 0 7557720Sgblack@eecs.umich.edu inst->setPredTarg(target); 7562935Sksewell@umich.edu break; 7572935Sksewell@umich.edu } 7582935Sksewell@umich.edu } 7591060SN/A } 7601061SN/A 7612292SN/A // If we didn't process all instructions, then we will need to block 7622292SN/A // and put all those instructions into the skid buffer. 7632292SN/A if (!insts_to_decode.empty()) { 7642292SN/A block(tid); 7652292SN/A } 7662292SN/A 7672292SN/A // Record that decode has written to the time buffer for activity 7682292SN/A // tracking. 7692292SN/A if (toRenameIndex) { 7702292SN/A wroteToTimeBuffer = true; 7712292SN/A } 7721060SN/A} 7739944Smatt.horsnell@ARM.com 7749944Smatt.horsnell@ARM.com#endif//__CPU_O3_DECODE_IMPL_HH__ 775