1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_DECODE_HH__
44#define __CPU_O3_DECODE_HH__
45
46#include <queue>
47
48#include "base/statistics.hh"
49#include "cpu/timebuf.hh"
50
51struct DerivO3CPUParams;
52
53/**
54 * DefaultDecode class handles both single threaded and SMT
55 * decode. Its width is specified by the parameters; each cycles it
56 * tries to decode that many instructions. Because instructions are
57 * actually decoded when the StaticInst is created, this stage does
58 * not do much other than check any PC-relative branches.
59 */
60template<class Impl>
61class DefaultDecode
62{
63  private:
64    // Typedefs from the Impl.
65    typedef typename Impl::O3CPU O3CPU;
66    typedef typename Impl::DynInstPtr DynInstPtr;
67    typedef typename Impl::CPUPol CPUPol;
68
69    // Typedefs from the CPU policy.
70    typedef typename CPUPol::FetchStruct FetchStruct;
71    typedef typename CPUPol::DecodeStruct DecodeStruct;
72    typedef typename CPUPol::TimeStruct TimeStruct;
73
74  public:
75    /** Overall decode stage status. Used to determine if the CPU can
76     * deschedule itself due to a lack of activity.
77     */
78    enum DecodeStatus {
79        Active,
80        Inactive
81    };
82
83    /** Individual thread status. */
84    enum ThreadStatus {
85        Running,
86        Idle,
87        StartSquash,
88        Squashing,
89        Blocked,
90        Unblocking
91    };
92
93  private:
94    /** Decode status. */
95    DecodeStatus _status;
96
97    /** Per-thread status. */
98    ThreadStatus decodeStatus[Impl::MaxThreads];
99
100  public:
101    /** DefaultDecode constructor. */
102    DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
103
104    void startupStage();
105
106    /** Clear all thread-specific states */
107    void clearStates(ThreadID tid);
108
109    void resetStage();
110
111    /** Returns the name of decode. */
112    std::string name() const;
113
114    /** Registers statistics. */
115    void regStats();
116
117    /** Sets the main backwards communication time buffer pointer. */
118    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
119
120    /** Sets pointer to time buffer used to communicate to the next stage. */
121    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
122
123    /** Sets pointer to time buffer coming from fetch. */
124    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
125
126    /** Sets pointer to list of active threads. */
127    void setActiveThreads(std::list<ThreadID> *at_ptr);
128
129    /** Perform sanity checks after a drain. */
130    void drainSanityCheck() const;
131
132    /** Has the stage drained? */
133    bool isDrained() const;
134
135    /** Takes over from another CPU's thread. */
136    void takeOverFrom() { resetStage(); }
137
138    /** Ticks decode, processing all input signals and decoding as many
139     * instructions as possible.
140     */
141    void tick();
142
143    /** Determines what to do based on decode's current status.
144     * @param status_change decode() sets this variable if there was a status
145     * change (ie switching from from blocking to unblocking).
146     * @param tid Thread id to decode instructions from.
147     */
148    void decode(bool &status_change, ThreadID tid);
149
150    /** Processes instructions from fetch and passes them on to rename.
151     * Decoding of instructions actually happens when they are created in
152     * fetch, so this function mostly checks if PC-relative branches are
153     * correct.
154     */
155    void decodeInsts(ThreadID tid);
156
157  private:
158    /** Inserts a thread's instructions into the skid buffer, to be decoded
159     * once decode unblocks.
160     */
161    void skidInsert(ThreadID tid);
162
163    /** Returns if all of the skid buffers are empty. */
164    bool skidsEmpty();
165
166    /** Updates overall decode status based on all of the threads' statuses. */
167    void updateStatus();
168
169    /** Separates instructions from fetch into individual lists of instructions
170     * sorted by thread.
171     */
172    void sortInsts();
173
174    /** Reads all stall signals from the backwards communication timebuffer. */
175    void readStallSignals(ThreadID tid);
176
177    /** Checks all input signals and updates decode's status appropriately. */
178    bool checkSignalsAndUpdate(ThreadID tid);
179
180    /** Checks all stall signals, and returns if any are true. */
181    bool checkStall(ThreadID tid) const;
182
183    /** Returns if there any instructions from fetch on this cycle. */
184    inline bool fetchInstsValid();
185
186    /** Switches decode to blocking, and signals back that decode has
187     * become blocked.
188     * @return Returns true if there is a status change.
189     */
190    bool block(ThreadID tid);
191
192    /** Switches decode to unblocking if the skid buffer is empty, and
193     * signals back that decode has unblocked.
194     * @return Returns true if there is a status change.
195     */
196    bool unblock(ThreadID tid);
197
198    /** Squashes if there is a PC-relative branch that was predicted
199     * incorrectly. Sends squash information back to fetch.
200     */
201    void squash(const DynInstPtr &inst, ThreadID tid);
202
203  public:
204    /** Squashes due to commit signalling a squash. Changes status to
205     * squashing and clears block/unblock signals as needed.
206     */
207    unsigned squash(ThreadID tid);
208
209  private:
210    // Interfaces to objects outside of decode.
211    /** CPU interface. */
212    O3CPU *cpu;
213
214    /** Time buffer interface. */
215    TimeBuffer<TimeStruct> *timeBuffer;
216
217    /** Wire to get rename's output from backwards time buffer. */
218    typename TimeBuffer<TimeStruct>::wire fromRename;
219
220    /** Wire to get iew's information from backwards time buffer. */
221    typename TimeBuffer<TimeStruct>::wire fromIEW;
222
223    /** Wire to get commit's information from backwards time buffer. */
224    typename TimeBuffer<TimeStruct>::wire fromCommit;
225
226    /** Wire to write information heading to previous stages. */
227    // Might not be the best name as not only fetch will read it.
228    typename TimeBuffer<TimeStruct>::wire toFetch;
229
230    /** Decode instruction queue. */
231    TimeBuffer<DecodeStruct> *decodeQueue;
232
233    /** Wire used to write any information heading to rename. */
234    typename TimeBuffer<DecodeStruct>::wire toRename;
235
236    /** Fetch instruction queue interface. */
237    TimeBuffer<FetchStruct> *fetchQueue;
238
239    /** Wire to get fetch's output from fetch queue. */
240    typename TimeBuffer<FetchStruct>::wire fromFetch;
241
242    /** Queue of all instructions coming from fetch this cycle. */
243    std::queue<DynInstPtr> insts[Impl::MaxThreads];
244
245    /** Skid buffer between fetch and decode. */
246    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
247
248    /** Variable that tracks if decode has written to the time buffer this
249     * cycle. Used to tell CPU if there is activity this cycle.
250     */
251    bool wroteToTimeBuffer;
252
253    /** Source of possible stalls. */
254    struct Stalls {
255        bool rename;
256    };
257
258    /** Tracks which stages are telling decode to stall. */
259    Stalls stalls[Impl::MaxThreads];
260
261    /** Rename to decode delay. */
262    Cycles renameToDecodeDelay;
263
264    /** IEW to decode delay. */
265    Cycles iewToDecodeDelay;
266
267    /** Commit to decode delay. */
268    Cycles commitToDecodeDelay;
269
270    /** Fetch to decode delay. */
271    Cycles fetchToDecodeDelay;
272
273    /** The width of decode, in instructions. */
274    unsigned decodeWidth;
275
276    /** Index of instructions being sent to rename. */
277    unsigned toRenameIndex;
278
279    /** number of Active Threads*/
280    ThreadID numThreads;
281
282    /** List of active thread ids */
283    std::list<ThreadID> *activeThreads;
284
285    /** Maximum size of the skid buffer. */
286    unsigned skidBufferMax;
287
288    /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/
289    Addr bdelayDoneSeqNum[Impl::MaxThreads];
290
291    /** Instruction used for squashing branch (used for MIPS)*/
292    DynInstPtr squashInst[Impl::MaxThreads];
293
294    /** Tells when their is a pending delay slot inst. to send
295     *  to rename. If there is, then wait squash after the next
296     *  instruction (used for MIPS).
297     */
298    bool squashAfterDelaySlot[Impl::MaxThreads];
299
300
301    /** Stat for total number of idle cycles. */
302    Stats::Scalar decodeIdleCycles;
303    /** Stat for total number of blocked cycles. */
304    Stats::Scalar decodeBlockedCycles;
305    /** Stat for total number of normal running cycles. */
306    Stats::Scalar decodeRunCycles;
307    /** Stat for total number of unblocking cycles. */
308    Stats::Scalar decodeUnblockCycles;
309    /** Stat for total number of squashing cycles. */
310    Stats::Scalar decodeSquashCycles;
311    /** Stat for number of times a branch is resolved at decode. */
312    Stats::Scalar decodeBranchResolved;
313    /** Stat for number of times a branch mispredict is detected. */
314    Stats::Scalar decodeBranchMispred;
315    /** Stat for number of times decode detected a non-control instruction
316     * incorrectly predicted as a branch.
317     */
318    Stats::Scalar decodeControlMispred;
319    /** Stat for total number of decoded instructions. */
320    Stats::Scalar decodeDecodedInsts;
321    /** Stat for total number of squashed instructions. */
322    Stats::Scalar decodeSquashedInsts;
323};
324
325#endif // __CPU_O3_DECODE_HH__
326