1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/kernel_stats.hh"
35#include "arch/alpha/osfpal.hh"
36#include "arch/alpha/tlb.hh"
37#include "base/cp_annotate.hh"
38#include "base/debug.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/thread_context.hh"
42#include "sim/sim_exit.hh"
43
44namespace AlphaISA {
45
46template<typename T>
47TLB *
48getITBPtr(T *tc)
49{
50    auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
51    assert(tlb);
52    return tlb;
53}
54
55template<typename T>
56TLB *
57getDTBPtr(T *tc)
58{
59    auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
60    assert(tlb);
61    return tlb;
62}
63
64////////////////////////////////////////////////////////////////////////
65//
66//  Machine dependent functions
67//
68void
69initCPU(ThreadContext *tc, int cpuId)
70{
71    initIPRs(tc, cpuId);
72
73    tc->setIntReg(16, cpuId);
74    tc->setIntReg(0, cpuId);
75
76    AlphaFault *reset = new ResetFault;
77
78    tc->pcState(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
79
80    delete reset;
81}
82
83template <class CPU>
84void
85zeroRegisters(CPU *cpu)
86{
87    // Insure ISA semantics
88    // (no longer very clean due to the change in setIntReg() in the
89    // cpu model.  Consider changing later.)
90    cpu->thread->setIntReg(ZeroReg, 0);
91    cpu->thread->setFloatReg(ZeroReg, 0);
92}
93
94////////////////////////////////////////////////////////////////////////
95//
96//
97//
98void
99initIPRs(ThreadContext *tc, int cpuId)
100{
101    for (int i = 0; i < NumInternalProcRegs; ++i) {
102        tc->setMiscRegNoEffect(i, 0);
103    }
104
105    tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
106    tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
107    tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
108}
109
110RegVal
111ISA::readIpr(int idx, ThreadContext *tc)
112{
113    uint64_t retval = 0;        // return value, default 0
114
115    switch (idx) {
116      case IPR_PALtemp0:
117      case IPR_PALtemp1:
118      case IPR_PALtemp2:
119      case IPR_PALtemp3:
120      case IPR_PALtemp4:
121      case IPR_PALtemp5:
122      case IPR_PALtemp6:
123      case IPR_PALtemp7:
124      case IPR_PALtemp8:
125      case IPR_PALtemp9:
126      case IPR_PALtemp10:
127      case IPR_PALtemp11:
128      case IPR_PALtemp12:
129      case IPR_PALtemp13:
130      case IPR_PALtemp14:
131      case IPR_PALtemp15:
132      case IPR_PALtemp16:
133      case IPR_PALtemp17:
134      case IPR_PALtemp18:
135      case IPR_PALtemp19:
136      case IPR_PALtemp20:
137      case IPR_PALtemp21:
138      case IPR_PALtemp22:
139      case IPR_PALtemp23:
140      case IPR_PAL_BASE:
141
142      case IPR_IVPTBR:
143      case IPR_DC_MODE:
144      case IPR_MAF_MODE:
145      case IPR_ISR:
146      case IPR_EXC_ADDR:
147      case IPR_IC_PERR_STAT:
148      case IPR_DC_PERR_STAT:
149      case IPR_MCSR:
150      case IPR_ASTRR:
151      case IPR_ASTER:
152      case IPR_SIRR:
153      case IPR_ICSR:
154      case IPR_ICM:
155      case IPR_DTB_CM:
156      case IPR_IPLR:
157      case IPR_INTID:
158      case IPR_PMCTR:
159        // no side-effect
160        retval = ipr[idx];
161        break;
162
163      case IPR_CC:
164        retval |= ipr[idx] & ULL(0xffffffff00000000);
165        retval |= tc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
166        break;
167
168      case IPR_VA:
169        retval = ipr[idx];
170        break;
171
172      case IPR_VA_FORM:
173      case IPR_MM_STAT:
174      case IPR_IFAULT_VA_FORM:
175      case IPR_EXC_MASK:
176      case IPR_EXC_SUM:
177        retval = ipr[idx];
178        break;
179
180      case IPR_DTB_PTE:
181        {
182            TlbEntry &entry = getDTBPtr(tc)->index(1);
183
184            retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
185            retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
186            retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
187            retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
188            retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
189            retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
190            retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
191        }
192        break;
193
194        // write only registers
195      case IPR_HWINT_CLR:
196      case IPR_SL_XMIT:
197      case IPR_DC_FLUSH:
198      case IPR_IC_FLUSH:
199      case IPR_ALT_MODE:
200      case IPR_DTB_IA:
201      case IPR_DTB_IAP:
202      case IPR_ITB_IA:
203      case IPR_ITB_IAP:
204        panic("Tried to read write only register %d\n", idx);
205        break;
206
207      default:
208        // invalid IPR
209        panic("Tried to read from invalid ipr %d\n", idx);
210        break;
211    }
212
213    return retval;
214}
215
216// Cause the simulator to break when changing to the following IPL
217int break_ipl = -1;
218
219void
220ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
221{
222    auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
223            tc->getKernelStats());
224    assert(stats || !tc->getKernelStats());
225    switch (idx) {
226      case IPR_PALtemp0:
227      case IPR_PALtemp1:
228      case IPR_PALtemp2:
229      case IPR_PALtemp3:
230      case IPR_PALtemp4:
231      case IPR_PALtemp5:
232      case IPR_PALtemp6:
233      case IPR_PALtemp7:
234      case IPR_PALtemp8:
235      case IPR_PALtemp9:
236      case IPR_PALtemp10:
237      case IPR_PALtemp11:
238      case IPR_PALtemp12:
239      case IPR_PALtemp13:
240      case IPR_PALtemp14:
241      case IPR_PALtemp15:
242      case IPR_PALtemp16:
243      case IPR_PALtemp17:
244      case IPR_PALtemp18:
245      case IPR_PALtemp19:
246      case IPR_PALtemp20:
247      case IPR_PALtemp21:
248      case IPR_PALtemp22:
249      case IPR_PAL_BASE:
250      case IPR_IC_PERR_STAT:
251      case IPR_DC_PERR_STAT:
252      case IPR_PMCTR:
253        // write entire quad w/ no side-effect
254        ipr[idx] = val;
255        break;
256
257      case IPR_CC_CTL:
258        // This IPR resets the cycle counter.  We assume this only
259        // happens once... let's verify that.
260        assert(ipr[idx] == 0);
261        ipr[idx] = 1;
262        break;
263
264      case IPR_CC:
265        // This IPR only writes the upper 64 bits.  It's ok to write
266        // all 64 here since we mask out the lower 32 in rpcc (see
267        // isa_desc).
268        ipr[idx] = val;
269        break;
270
271      case IPR_PALtemp23:
272        // write entire quad w/ no side-effect
273        if (stats)
274            stats->context(ipr[idx], val, tc);
275        ipr[idx] = val;
276        break;
277
278      case IPR_DTB_PTE:
279        // write entire quad w/ no side-effect, tag is forthcoming
280        ipr[idx] = val;
281        break;
282
283      case IPR_EXC_ADDR:
284        // second least significant bit in PC is always zero
285        ipr[idx] = val & ~2;
286        break;
287
288      case IPR_ASTRR:
289      case IPR_ASTER:
290        // only write least significant four bits - privilege mask
291        ipr[idx] = val & 0xf;
292        break;
293
294      case IPR_IPLR:
295        // only write least significant five bits - interrupt level
296        ipr[idx] = val & 0x1f;
297        if (stats)
298            stats->swpipl(ipr[idx]);
299        break;
300
301      case IPR_DTB_CM:
302        if (val & 0x18) {
303            if (stats)
304                stats->mode(Kernel::user, tc);
305        } else {
306            if (stats)
307                stats->mode(Kernel::kernel, tc);
308        }
309        M5_FALLTHROUGH;
310
311      case IPR_ICM:
312        // only write two mode bits - processor mode
313        ipr[idx] = val & 0x18;
314        break;
315
316      case IPR_ALT_MODE:
317        // only write two mode bits - processor mode
318        ipr[idx] = val & 0x18;
319        break;
320
321      case IPR_MCSR:
322        // more here after optimization...
323        ipr[idx] = val;
324        break;
325
326      case IPR_SIRR:
327        // only write software interrupt mask
328        ipr[idx] = val & 0x7fff0;
329        break;
330
331      case IPR_ICSR:
332        ipr[idx] = val & ULL(0xffffff0300);
333        break;
334
335      case IPR_IVPTBR:
336      case IPR_MVPTBR:
337        ipr[idx] = val & ULL(0xffffffffc0000000);
338        break;
339
340      case IPR_DC_TEST_CTL:
341        ipr[idx] = val & 0x1ffb;
342        break;
343
344      case IPR_DC_MODE:
345      case IPR_MAF_MODE:
346        ipr[idx] = val & 0x3f;
347        break;
348
349      case IPR_ITB_ASN:
350        ipr[idx] = val & 0x7f0;
351        break;
352
353      case IPR_DTB_ASN:
354        ipr[idx] = val & ULL(0xfe00000000000000);
355        break;
356
357      case IPR_EXC_SUM:
358      case IPR_EXC_MASK:
359        // any write to this register clears it
360        ipr[idx] = 0;
361        break;
362
363      case IPR_INTID:
364      case IPR_SL_RCV:
365      case IPR_MM_STAT:
366      case IPR_ITB_PTE_TEMP:
367      case IPR_DTB_PTE_TEMP:
368        // read-only registers
369        panic("Tried to write read only ipr %d\n", idx);
370
371      case IPR_HWINT_CLR:
372      case IPR_SL_XMIT:
373      case IPR_DC_FLUSH:
374      case IPR_IC_FLUSH:
375        // the following are write only
376        ipr[idx] = val;
377        break;
378
379      case IPR_DTB_IA:
380        // really a control write
381        ipr[idx] = 0;
382
383        getDTBPtr(tc)->flushAll();
384        break;
385
386      case IPR_DTB_IAP:
387        // really a control write
388        ipr[idx] = 0;
389
390        getDTBPtr(tc)->flushProcesses();
391        break;
392
393      case IPR_DTB_IS:
394        // really a control write
395        ipr[idx] = val;
396
397        getDTBPtr(tc)->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
398        break;
399
400      case IPR_DTB_TAG: {
401          struct TlbEntry entry;
402
403          // FIXME: granularity hints NYI...
404          if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
405              panic("PTE GH field != 0");
406
407          // write entire quad
408          ipr[idx] = val;
409
410          // construct PTE for new entry
411          entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
412          entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
413          entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
414          entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
415          entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
416          entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
417          entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
418
419          // insert new TAG/PTE value into data TLB
420          getDTBPtr(tc)->insert(val, entry);
421      }
422        break;
423
424      case IPR_ITB_PTE: {
425          struct TlbEntry entry;
426
427          // FIXME: granularity hints NYI...
428          if (ITB_PTE_GH(val) != 0)
429              panic("PTE GH field != 0");
430
431          // write entire quad
432          ipr[idx] = val;
433
434          // construct PTE for new entry
435          entry.ppn = ITB_PTE_PPN(val);
436          entry.xre = ITB_PTE_XRE(val);
437          entry.xwe = 0;
438          entry.fonr = ITB_PTE_FONR(val);
439          entry.fonw = ITB_PTE_FONW(val);
440          entry.asma = ITB_PTE_ASMA(val);
441          entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
442
443          // insert new TAG/PTE value into data TLB
444          getITBPtr(tc)->insert(ipr[IPR_ITB_TAG], entry);
445      }
446        break;
447
448      case IPR_ITB_IA:
449        // really a control write
450        ipr[idx] = 0;
451
452        getITBPtr(tc)->flushAll();
453        break;
454
455      case IPR_ITB_IAP:
456        // really a control write
457        ipr[idx] = 0;
458
459        getITBPtr(tc)->flushProcesses();
460        break;
461
462      case IPR_ITB_IS:
463        // really a control write
464        ipr[idx] = val;
465
466        getITBPtr(tc)->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
467        break;
468
469      default:
470        // invalid IPR
471        panic("Tried to write to invalid ipr %d\n", idx);
472    }
473
474    // no error...
475}
476
477void
478copyIprs(ThreadContext *src, ThreadContext *dest)
479{
480    for (int i = 0; i < NumInternalProcRegs; ++i)
481        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
482}
483
484} // namespace AlphaISA
485