Searched hist:2011 (Results 676 - 700 of 897) sorted by relevance
/gem5/tests/configs/ | ||
H A D | tsunami-simple-atomic.py | 8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues. 7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately. This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches. |
H A D | tsunami-simple-timing.py | 8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues. 7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately. This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches. |
H A D | rubytest-ruby.py | 8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch. 8322:19949c6de823 Mon May 23 17:29:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> config: tweak ruby configs to clean up hierarchy Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first. |
H A D | simple-timing-mp-ruby.py | 8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch. 8322:19949c6de823 Mon May 23 17:29:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> config: tweak ruby configs to clean up hierarchy Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first. |
/gem5/src/arch/alpha/ | ||
H A D | types.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8181:f789b9aac5f4 Sat Mar 26 09:23:00 EDT 2011 Korey Sewell <ksewell@umich.edu> mips: cleanup ISA-specific code *** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway. |
H A D | isa_traits.hh | 8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh. 8542:7230ff0738e3 Fri Sep 09 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> StaticInst: Merge StaticInst and StaticInstBase. Having two StaticInst classes, one nominally ISA dependent and the other ISA dependent, has not been historically useful and makes the StaticInst class more complicated that it needs to be. This change merges StaticInstBase into StaticInst. |
H A D | system.cc | 8741:491297d019f3 Fri Sep 30 03:29:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Remove System::platform and Platform::intrFrequency. In order for a system object to work in SE mode and FS mode, it has to either always require a platform object even in SE mode, or get rid of the requirement all together. Making SE mode carry around unnecessary/unused bits of FS seems less than ideal, so I decided to go with the second option. The platform pointer in the System class was used for exactly one purpose, a path for the Alpha Linux system object to get to the real time clock and read its frequency so that it could short cut the loops_per_jiffy calculation. There was also a copy and pasted implementation in MIPS, but since it was only there because it was there in Alpha I still count that as one use. This change reverses the mechanism that communicates the RTC frequency so that the Tsunami platform object pushes it up to the AlphaSystem object. This is slightly less specific than it could be because really only the AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform class was no longer necessary (and unimplemented on anything but Alpha) it was eliminated. After this change, a platform will need to have a system, but a system won't have to have a platform. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
H A D | utility.cc | 8780:89e0822462a1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of uses of FULL_SYSTEM in Alpha. 8300:eb279d6e08a2 Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and ExecKernel are set by default when Exec is specified. Use minus sign with ExecUser or ExecKernel to remove user or kernel tracing respectively. |
/gem5/src/arch/sparc/isa/formats/ | ||
H A D | branch.isa | 8345:9bb24e6edc35 Fri Jun 10 22:15:00 EDT 2011 Korey Sewell <ksewell@umich.edu> sparc: don't use directcntrl branch flag this flag is only used for early branch resolution in the O3 model (of pc-relative branches) but this isnt cleanly working even when the branch target code is added for sparc. For now, we'll ignore this optimization and add a todo in the SPARC ISA for future developers 8342:77d12d8f7971 Thu Jun 09 01:34:00 EDT 2011 Korey Sewell <ksewell@umich.edu> sparc: compilation fixes for inorder Add a few constants and functions that the InOrder model wants for SPARC. * * * sparc: add eaComp function InOrder separates the address generation from the actual access so give Sparc that functionality * * * sparc: add control flags for branches branch predictors and other cpu model functions need to know specific information about branches, so add the necessary flags here |
H A D | basic.isa | 8624:a1fca799b981 Mon Nov 28 04:35:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Minor style fix. I forgot to fix this as well per Ali's feedback. 8621:2a6d9a7197fe Sun Nov 27 22:00:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Isolate FP operations enough to prevent code/rounding mode reordering. |
/gem5/src/arch/x86/ | ||
H A D | faults.cc | 8740:253aeee61e66 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Remove FULL_SYSTEM from the x86 faults. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
H A D | system.cc | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7901:f9b675da608a Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: implements vtophys Calls walker to look up virt. to phys. page mapping |
/gem5/src/cpu/o3/ | ||
H A D | commit.hh | 8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 8230:845c8eb5ac49 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: fix up code after sorting 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8137:48371b9fb929 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Cleanup the commitInfo comm struct. Get rid of unused members and use base types rather than derrived values where possible to limit amount of state. 7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters Updated patches from Rick Strong's set that modify performance counters for McPAT 7855:c0be563517da Tue Jan 18 17:30:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Keep around the last committed instruction and use for squashing. Without this change 0 is always used for the youngest sequence number if a squash occured and the ROB was empty (E.g. an instruction is marked serializeAfter or a fetch stall prevents other instructions from issuing). Using 0 there is a race to rename where an instruction that committed the same cycle as the squashing instruction can have it's renamed state undone by the squash using sequence number 0. 7847:0c6613ad8f18 Tue Jan 18 17:30:00 EST 2011 Min Kyu Jeong <minkyu.jeong@arm.com> O3: Fixes fetch deadlock when the interrupt clears before CPU handles it. When this condition occurs the cpu should restart the fetch stage to fetch from the original execution path. Fault handling in the commit stage is cleaned up a little bit so the control flow is simplier. Finally, if an instruction is being used to carry a fault it isn't executed, so the fault propagates appropriately. 7813:7338bc628489 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Move sched_list.hh and timebuf.hh from src/base to src/cpu. These files really aren't general enough to belong in src/base. This patch doesn't reorder include lines, leaving them unsorted in many cases, but Nate's magic script will fix that up shortly. |
H A D | rob.hh | 8230:845c8eb5ac49 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: fix up code after sorting 7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters Updated patches from Rick Strong's set that modify performance counters for McPAT |
H A D | rename_map.cc | 8346:ce8b9a250021 Fri Jun 10 22:15:00 EDT 2011 Korey Sewell <ksewell@umich.edu> o3: missing newlines on some dprintfs 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
/gem5/src/mem/cache/prefetch/ | ||
H A D | stride.cc | 8509:afb40c3d4ba6 Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Prefetcher: Fix some memory leaks with the prefetcher. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
/gem5/src/sim/ | ||
H A D | sim_events.hh | 7821:f1d298b7416c Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> sim: clean up CountedDrainEvent slightly. There's no reason for it to derive from SimLoopExitEvent. This whole drain thing needs to be redone eventually, but this is a stopgap to make later changes to SimLoopExitEvent feasible. 7820:4ee66d8c1dd8 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> sim: delete unused CheckSwapEvent code. There's no way to even create one of these anymore. |
H A D | system.hh | 8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh. 8769:f95b2a679eb0 Sun Oct 30 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the system object more consistent between SE and FS. 8765:659670964330 Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make some system funcs available in SE and FS. 8741:491297d019f3 Fri Sep 30 03:29:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Remove System::platform and Platform::intrFrequency. In order for a system object to work in SE mode and FS mode, it has to either always require a platform object even in SE mode, or get rid of the requirement all together. Making SE mode carry around unnecessary/unused bits of FS seems less than ideal, so I decided to go with the second option. The platform pointer in the System class was used for exactly one purpose, a path for the Alpha Linux system object to get to the real time clock and read its frequency so that it could short cut the loops_per_jiffy calculation. There was also a copy and pasted implementation in MIPS, but since it was only there because it was there in Alpha I still count that as one use. This change reverses the mechanism that communicates the RTC frequency so that the Tsunami platform object pushes it up to the AlphaSystem object. This is slightly less specific than it could be because really only the AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform class was no longer necessary (and unimplemented on anything but Alpha) it was eliminated. After this change, a platform will need to have a system, but a system won't have to have a platform. 8601:af28085882dc Sun Oct 23 01:30:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> SE: move page allocation from PageTable to Process PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable. The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process. 8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation. 7914:eee5bb0fb8ea Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> m5: added work completed monitoring support 7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters Updated patches from Rick Strong's set that modify performance counters for McPAT |
H A D | system.cc | 8769:f95b2a679eb0 Sun Oct 30 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the system object more consistent between SE and FS. 8765:659670964330 Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make some system funcs available in SE and FS. 8601:af28085882dc Sun Oct 23 01:30:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> SE: move page allocation from PageTable to Process PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable. The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process. 8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7914:eee5bb0fb8ea Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> m5: added work completed monitoring support 7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters Updated patches from Rick Strong's set that modify performance counters for McPAT |
/gem5/configs/example/ | ||
H A D | fs.py | 8635:23ba076b2cca Thu Dec 01 03:15:00 EST 2011 Chris Emmons <chris.emmons@arm.com> VNC: Add support for capturing frame buffer to file each time it is changed. When a change in the frame buffer from the VNC server is detected, the new frame is stored out to the m5out/frames_*/ directory. Specifiy the flag "--frame-capture" when running configs/example/fs.py to enable this behavior. 8354:26be660e365a Fri Jun 17 01:20:00 EDT 2011 Gedare Bloom <gedare@gwmail.gwu.edu> ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. 8061:08e91664adac Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Clarifies creation of Linux and baremetal ARM systems. makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems. 7925:6823ef6d7a9f Mon Feb 07 04:22:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86, Config: Move the setting of work count options to a separate function. This way things that don't care about work count options and/or aren't called by something that has those command line options set up doesn't have to build a fake object to carry in inert values. 7914:eee5bb0fb8ea Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> m5: added work completed monitoring support 7877:19beb0676222 Thu Feb 03 23:56:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Mem,X86: Make the IO bridge pass APIC messages back towards the CPU. 7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately. This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches. 7861:4ebff121cc0e Wed Jan 19 14:48:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Time: Add a mechanism to prevent M5 from running faster than real time. M5 skips over any simulated time where it doesn't have any work to do. When the simulation is active, the time skipped is short and the work done at any point in time is relatively substantial. If the time between events is long and/or the work to do at each event is small, it's possible for simulated time to pass faster than real time. When running a benchmark that can be good because it means the simulation will finish sooner in real time. When interacting with the real world through, for instance, a serial terminal or bridge to a real network, this can be a problem. Human or network response time could be greatly exagerated from the perspective of the simulation and make simulated events happen "too soon" from an external perspective. This change adds the capability to force the simulation to run no faster than real time. It does so by scheduling a periodic event that checks to see if its simulated period is shorter than its real period. If it is, it stalls the simulation until they're equal. This is called time syncing. A future change could add pseudo instructions which turn time syncing on and off from within the simulation. That would allow time syncing to be used for the interactive parts of a session but then turned off when running a benchmark using the m5 utility program inside a script. Time syncing would probably not happen anyway while running a benchmark because there would be plenty of work for M5 to do, but the event overhead could be avoided. |
/gem5/src/arch/mips/ | ||
H A D | mt.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
/gem5/src/cpu/testers/memtest/ | ||
H A D | memtest.hh | 8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/cpu/ | ||
H A D | thread_context.cc | 8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
/gem5/src/mem/ | ||
H A D | tport.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
/gem5/src/python/m5/ | ||
H A D | params.py | 8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1. And by "everything" I mean all the quick regressions. 8597:45c9f664a365 Thu Oct 20 16:09:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> SimObject: add export_method* hooks to export C++ methods to Python Replace the (broken as of previous changeset) swig_objdecl() method that allowed/forced you to substitute a whole new C++ struct definition for SWIG to wrap with a set of export_method* hooks that let you just declare a set of C++ methods (or other declarations) that get inserted in the auto-generated struct. Restore the System get/setMemoryMode methods, and use this mechanism to specialize SimObject as well, eliminating teh need for sim_object.i. Needed bits of sim_object.i are moved to the new pyobject.i. Also sucked a little SimObject specialization into cxx_param_decl() allowing us to get rid of src/sim/sim_object_params.hh. Now the generation and wrapping of the base SimObject param struct is more in line with how derived objects are handled. 8596:e6e22fa77883 Thu Oct 20 16:08:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons/swig: refactor some of the scons/SWIG code - Move the random bits of SWIG code generation out of src/SConscript file and into methods on the objects being wrapped. - Cleaned up some variable naming and added some comments to make the process a little clearer. - Did a little generated file/module renaming: - vptype_Foo now Foo_vector - init_Foo is now Foo_init This makes it easier to see all the Foo-related files in a sorted directory listing. - Made cxx_predecls and swig_predecls normal SimObject classmethods. - Got rid of swig_objdecls hook, even though this breaks the System objects get/setMemoryMode method exports. Will be fixing this in a future changeset. 8579:ad3704c8a503 Thu Sep 22 21:58:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> params.py: enhance IpAddress param handling Print IpAddress params in dot notation for readability. Properly compare IpAddress objects (by value and not object identity). Also fix up derived param classes (IpNetmask and IpWithPort) similarly. 8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation. 8459:b8c3c20d0385 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Config: Add support for a Self.all proxy object 8321:9f34cf472451 Mon May 23 17:29:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> config: reinstate implicit parenting on parameter assignment Last summer's big rewrite of the initialization code (in particular cset 6efc3672733b) got rid of the implicit parenting that used to occur when an unparented SimObject was assigned as a parameter value to another SimObject. The idea was that the new adoptOrphanParams() step would catch these anyway so it was unnecessary. Unfortunately it turns out that adoptOrphanParams() has some inherent instability in that the parent that does the adoption depends on the config tree traversal order. Even making this order deterministic (e.g., by traversing children in alphabetical order) can introduce unwanted and unexpected hierarchy changes between similar configs (e.g., when adding a switch_cpu in place of a cpu), causing problems when trying to restore checkpoints across similar configs. The hierarchy created by implicit parenting is more stable and more controllable, so this patch turns that behavior back on. This patch also cleans up some long-standing holes regarding parenting of SimObjects that are created in class definitions (either in the body of the class, or as default parameters). To avoid breaking some existing config files, this necessitated changing the error on reparenting children to a warning. This change fixes another bug where attempting to print the prior error message would fail on reparenting SimObjectVectors because they lack a _parent attribute. Some further issues with SimObjectVectors were cleaned up by getting rid of the get_parent() call (which could cause errors with some SimObjectVectors where there was no single parent to return) with has_parent() (since all the uses of get_parent() were just boolean tests anyway). Finally, since the adoptOrphanParam() step turned out to be so problematic, we now issue a warning when it actually has to do an adoption. Future cleanup of config files will get rid of current warnings. 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
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