11689SN/A/* 210331Smitch.hayenga@arm.com * Copyright (c) 2010-2012, 2014 ARM Limited 37855SAli.Saidi@ARM.com * All rights reserved. 47855SAli.Saidi@ARM.com * 57855SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67855SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77855SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87855SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97855SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107855SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117855SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127855SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137855SAli.Saidi@ARM.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_COMMIT_HH__ 452292SN/A#define __CPU_O3_COMMIT_HH__ 461060SN/A 478230Snate@binkert.org#include <queue> 488230Snate@binkert.org 491461SN/A#include "base/statistics.hh" 502292SN/A#include "cpu/exetrace.hh" 512329SN/A#include "cpu/inst_seq.hh" 528229Snate@binkert.org#include "cpu/timebuf.hh" 5313563Snikos.nikoleris@arm.com#include "enums/CommitPolicy.hh" 5410023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh" 551060SN/A 568737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 575529Snate@binkert.org 582292SN/Atemplate <class> 598737Skoansin.tan@gmail.comstruct O3ThreadState; 602292SN/A 612292SN/A/** 622316SN/A * DefaultCommit handles single threaded and SMT commit. Its width is 632316SN/A * specified by the parameters; each cycle it tries to commit that 642316SN/A * many instructions. The SMT policy decides which thread it tries to 652316SN/A * commit instructions from. Non- speculative instructions must reach 662316SN/A * the head of the ROB before they are ready to execute; once they 672316SN/A * reach the head, commit will broadcast the instruction's sequence 682316SN/A * number to the previous stages so that they can issue/ execute the 692316SN/A * instruction. Only one non-speculative instruction is handled per 702316SN/A * cycle. Commit is responsible for handling all back-end initiated 712316SN/A * redirects. It receives the redirect, and then broadcasts it to all 722316SN/A * stages, indicating the sequence number they should squash until, 732316SN/A * and any necessary branch misprediction information as well. It 742316SN/A * priortizes redirects by instruction's age, only broadcasting a 752316SN/A * redirect if it corresponds to an instruction that should currently 762316SN/A * be in the ROB. This is done by tracking the sequence number of the 772316SN/A * youngest instruction in the ROB, which gets updated to any 782316SN/A * squashing instruction's sequence number, and only broadcasting a 792316SN/A * redirect if it corresponds to an older instruction. Commit also 802316SN/A * supports multiple cycle squashing, to model a ROB that can only 812329SN/A * remove a certain number of instructions per cycle. 822292SN/A */ 831060SN/Atemplate<class Impl> 842292SN/Aclass DefaultCommit 851060SN/A{ 861060SN/A public: 871060SN/A // Typedefs from the Impl. 882733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 891061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 901061SN/A typedef typename Impl::CPUPol CPUPol; 911060SN/A 922292SN/A typedef typename CPUPol::RenameMap RenameMap; 931061SN/A typedef typename CPUPol::ROB ROB; 941060SN/A 951061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 962292SN/A typedef typename CPUPol::FetchStruct FetchStruct; 971061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 981061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 991060SN/A 1002316SN/A typedef typename CPUPol::Fetch Fetch; 1012292SN/A typedef typename CPUPol::IEW IEW; 1022292SN/A 1032292SN/A typedef O3ThreadState<Impl> Thread; 1042292SN/A 1052292SN/A /** Overall commit status. Used to determine if the CPU can deschedule 1062292SN/A * itself due to a lack of activity. 1072292SN/A */ 1082292SN/A enum CommitStatus{ 1092292SN/A Active, 1102292SN/A Inactive 1112292SN/A }; 1122292SN/A 1132292SN/A /** Individual thread status. */ 1142292SN/A enum ThreadStatus { 1151060SN/A Running, 1161060SN/A Idle, 1171060SN/A ROBSquashing, 1182292SN/A TrapPending, 1199437SAndreas.Sandberg@ARM.com FetchTrapPending, 1209437SAndreas.Sandberg@ARM.com SquashAfterPending, //< Committing instructions before a squash. 1212292SN/A }; 1222292SN/A 1231060SN/A private: 1242292SN/A /** Overall commit status. */ 1252292SN/A CommitStatus _status; 1262292SN/A /** Next commit status, to be set at the end of the cycle. */ 1272292SN/A CommitStatus _nextStatus; 1282292SN/A /** Per-thread status. */ 1292292SN/A ThreadStatus commitStatus[Impl::MaxThreads]; 1302292SN/A /** Commit policy used in SMT mode. */ 1312292SN/A CommitPolicy commitPolicy; 1321060SN/A 13310023Smatt.horsnell@ARM.com /** Probe Points. */ 13410023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppCommit; 13510023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppCommitStall; 13611246Sradhika.jagtap@ARM.com /** To probe when an instruction is squashed */ 13711246Sradhika.jagtap@ARM.com ProbePointArg<DynInstPtr> *ppSquash; 13810023Smatt.horsnell@ARM.com 13912127Sspwilson2@wisc.edu /** Mark the thread as processing a trap. */ 14012127Sspwilson2@wisc.edu void processTrapEvent(ThreadID tid); 14112127Sspwilson2@wisc.edu 1421060SN/A public: 1432292SN/A /** Construct a DefaultCommit with the given parameters. */ 1445529Snate@binkert.org DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params); 1451060SN/A 1462292SN/A /** Returns the name of the DefaultCommit. */ 1472292SN/A std::string name() const; 1482292SN/A 1492292SN/A /** Registers statistics. */ 1501062SN/A void regStats(); 1511062SN/A 15210023Smatt.horsnell@ARM.com /** Registers probes. */ 15310023Smatt.horsnell@ARM.com void regProbePoints(); 15410023Smatt.horsnell@ARM.com 1552292SN/A /** Sets the list of threads. */ 1562292SN/A void setThreads(std::vector<Thread *> &threads); 1572292SN/A 1582292SN/A /** Sets the main time buffer pointer, used for backwards communication. */ 1591060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1601060SN/A 1612292SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1622292SN/A 1632292SN/A /** Sets the pointer to the queue coming from rename. */ 1641060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1651060SN/A 1662292SN/A /** Sets the pointer to the queue coming from IEW. */ 1671060SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1681060SN/A 1692348SN/A /** Sets the pointer to the IEW stage. */ 1702292SN/A void setIEWStage(IEW *iew_stage); 1712292SN/A 1722316SN/A /** The pointer to the IEW stage. Used solely to ensure that 1732316SN/A * various events (traps, interrupts, syscalls) do not occur until 1742316SN/A * all stores have written back. 1752292SN/A */ 1762292SN/A IEW *iewStage; 1772292SN/A 1782292SN/A /** Sets pointer to list of active threads. */ 1796221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1802292SN/A 1812292SN/A /** Sets pointer to the commited state rename map. */ 1822292SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1832292SN/A 1842292SN/A /** Sets pointer to the ROB. */ 1851060SN/A void setROB(ROB *rob_ptr); 1861060SN/A 1872292SN/A /** Initializes stage by sending back the number of free entries. */ 1889427SAndreas.Sandberg@ARM.com void startupStage(); 1892292SN/A 19013641Sqtt2@cornell.edu /** Clear all thread-specific states */ 19113641Sqtt2@cornell.edu void clearStates(ThreadID tid); 19213641Sqtt2@cornell.edu 1932843Sktlim@umich.edu /** Initializes the draining of commit. */ 1949444SAndreas.Sandberg@ARM.com void drain(); 1952843Sktlim@umich.edu 1962843Sktlim@umich.edu /** Resumes execution after draining. */ 1979444SAndreas.Sandberg@ARM.com void drainResume(); 1982307SN/A 1999444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 2009444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2019444SAndreas.Sandberg@ARM.com 2029444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 2039444SAndreas.Sandberg@ARM.com bool isDrained() const; 2042316SN/A 2052348SN/A /** Takes over from another CPU's thread. */ 2062307SN/A void takeOverFrom(); 2072307SN/A 20810331Smitch.hayenga@arm.com /** Deschedules a thread from scheduling */ 20910331Smitch.hayenga@arm.com void deactivateThread(ThreadID tid); 21010331Smitch.hayenga@arm.com 2112292SN/A /** Ticks the commit stage, which tries to commit instructions. */ 2121060SN/A void tick(); 2131060SN/A 2142292SN/A /** Handles any squashes that are sent from IEW, and adds instructions 2152292SN/A * to the ROB and tries to commit instructions. 2162292SN/A */ 2171060SN/A void commit(); 2181060SN/A 2192292SN/A /** Returns the number of free ROB entries for a specific thread. */ 2206221Snate@binkert.org size_t numROBFreeEntries(ThreadID tid); 2212292SN/A 2222348SN/A /** Generates an event to schedule a squash due to a trap. */ 22311877Sbrandon.potter@amd.com void generateTrapEvent(ThreadID tid, Fault inst_fault); 2242348SN/A 2252348SN/A /** Records that commit needs to initiate a squash due to an 2262680Sktlim@umich.edu * external state update through the TC. 2272348SN/A */ 2286221Snate@binkert.org void generateTCEvent(ThreadID tid); 2292292SN/A 2301060SN/A private: 2312292SN/A /** Updates the overall status of commit with the nextStatus, and 2322348SN/A * tell the CPU if commit is active/inactive. 2332348SN/A */ 2342292SN/A void updateStatus(); 2351060SN/A 2362292SN/A /** Returns if any of the threads have the number of ROB entries changed 2372292SN/A * on this cycle. Used to determine if the number of free ROB entries needs 2382292SN/A * to be sent back to previous stages. 2392292SN/A */ 2402292SN/A bool changedROBEntries(); 2412292SN/A 2422348SN/A /** Squashes all in flight instructions. */ 2436221Snate@binkert.org void squashAll(ThreadID tid); 2442316SN/A 2452348SN/A /** Handles squashing due to a trap. */ 2466221Snate@binkert.org void squashFromTrap(ThreadID tid); 2472292SN/A 2482680Sktlim@umich.edu /** Handles squashing due to an TC write. */ 2496221Snate@binkert.org void squashFromTC(ThreadID tid); 2502292SN/A 2519437SAndreas.Sandberg@ARM.com /** Handles a squash from a squashAfter() request. */ 2529437SAndreas.Sandberg@ARM.com void squashFromSquashAfter(ThreadID tid); 2539437SAndreas.Sandberg@ARM.com 2549437SAndreas.Sandberg@ARM.com /** 2559437SAndreas.Sandberg@ARM.com * Handle squashing from instruction with SquashAfter set. 2569437SAndreas.Sandberg@ARM.com * 2577784SAli.Saidi@ARM.com * This differs from the other squashes as it squashes following 2587784SAli.Saidi@ARM.com * instructions instead of the current instruction and doesn't 2599437SAndreas.Sandberg@ARM.com * clean up various status bits about traps/tc writes 2609437SAndreas.Sandberg@ARM.com * pending. Since there might have been instructions committed by 2619437SAndreas.Sandberg@ARM.com * the commit stage before the squashing instruction was reached 2629437SAndreas.Sandberg@ARM.com * and we can't commit and squash in the same cycle, we have to 2639437SAndreas.Sandberg@ARM.com * squash in two steps: 2649437SAndreas.Sandberg@ARM.com * 2659437SAndreas.Sandberg@ARM.com * <ol> 2669437SAndreas.Sandberg@ARM.com * <li>Immediately set the commit status of the thread of 2679437SAndreas.Sandberg@ARM.com * SquashAfterPending. This forces the thread to stop 2689437SAndreas.Sandberg@ARM.com * committing instructions in this cycle. The last 2699437SAndreas.Sandberg@ARM.com * instruction to be committed in this cycle will be the 2709437SAndreas.Sandberg@ARM.com * SquashAfter instruction. 2719437SAndreas.Sandberg@ARM.com * <li>In the next cycle, commit() checks for the 2729437SAndreas.Sandberg@ARM.com * SquashAfterPending state and squashes <i>all</i> 2739437SAndreas.Sandberg@ARM.com * in-flight instructions. Since the SquashAfter instruction 2749437SAndreas.Sandberg@ARM.com * was the last instruction to be committed in the previous 2759437SAndreas.Sandberg@ARM.com * cycle, this causes all subsequent instructions to be 2769437SAndreas.Sandberg@ARM.com * squashed. 2779437SAndreas.Sandberg@ARM.com * </ol> 2789437SAndreas.Sandberg@ARM.com * 2799437SAndreas.Sandberg@ARM.com * @param tid ID of the thread to squash. 2809437SAndreas.Sandberg@ARM.com * @param head_inst Instruction that requested the squash. 2817784SAli.Saidi@ARM.com */ 28213429Srekai.gonzalezalberquilla@arm.com void squashAfter(ThreadID tid, const DynInstPtr &head_inst); 2837784SAli.Saidi@ARM.com 2844035Sktlim@umich.edu /** Handles processing an interrupt. */ 2854035Sktlim@umich.edu void handleInterrupt(); 2867847Sminkyu.jeong@arm.com 2877847Sminkyu.jeong@arm.com /** Get fetch redirecting so we can handle an interrupt */ 2887847Sminkyu.jeong@arm.com void propagateInterrupt(); 2894035Sktlim@umich.edu 2902292SN/A /** Commits as many instructions as possible. */ 2911060SN/A void commitInsts(); 2921060SN/A 2932292SN/A /** Tries to commit the head ROB instruction passed in. 2942292SN/A * @param head_inst The instruction to be committed. 2952292SN/A */ 29613429Srekai.gonzalezalberquilla@arm.com bool commitHead(const DynInstPtr &head_inst, unsigned inst_num); 2971060SN/A 2982292SN/A /** Gets instructions from rename and inserts them into the ROB. */ 2991060SN/A void getInsts(); 3001060SN/A 3012292SN/A /** Marks completed instructions using information sent from IEW. */ 3021060SN/A void markCompletedInsts(); 3031060SN/A 3042292SN/A /** Gets the thread to commit, based on the SMT policy. */ 3056221Snate@binkert.org ThreadID getCommittingThread(); 3062292SN/A 3072292SN/A /** Returns the thread ID to use based on a round robin policy. */ 3086221Snate@binkert.org ThreadID roundRobin(); 3092292SN/A 3102292SN/A /** Returns the thread ID to use based on an oldest instruction policy. */ 3116221Snate@binkert.org ThreadID oldestReady(); 3122292SN/A 3131684SN/A public: 3147720Sgblack@eecs.umich.edu /** Reads the PC of a specific thread. */ 3157720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid) { return pc[tid]; } 3167720Sgblack@eecs.umich.edu 3177720Sgblack@eecs.umich.edu /** Sets the PC of a specific thread. */ 3187720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val, ThreadID tid) 3197720Sgblack@eecs.umich.edu { pc[tid] = val; } 3201684SN/A 3212348SN/A /** Returns the PC of a specific thread. */ 3227720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); } 3232292SN/A 3247720Sgblack@eecs.umich.edu /** Returns the next PC of a specific thread. */ 3257720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); } 3264636Sgblack@eecs.umich.edu 3274636Sgblack@eecs.umich.edu /** Reads the micro PC of a specific thread. */ 3287720Sgblack@eecs.umich.edu Addr microPC(ThreadID tid) { return pc[tid].microPC(); } 3292756Sksewell@umich.edu 3301684SN/A private: 3311060SN/A /** Time buffer interface. */ 3321060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3331060SN/A 3341060SN/A /** Wire to write information heading to previous stages. */ 3351060SN/A typename TimeBuffer<TimeStruct>::wire toIEW; 3361060SN/A 3371060SN/A /** Wire to read information from IEW (for ROB). */ 3381060SN/A typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 3391060SN/A 3402292SN/A TimeBuffer<FetchStruct> *fetchQueue; 3412292SN/A 3422292SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 3432292SN/A 3441060SN/A /** IEW instruction queue interface. */ 3451060SN/A TimeBuffer<IEWStruct> *iewQueue; 3461060SN/A 3471060SN/A /** Wire to read information from IEW queue. */ 3481060SN/A typename TimeBuffer<IEWStruct>::wire fromIEW; 3491060SN/A 3501060SN/A /** Rename instruction queue interface, for ROB. */ 3511060SN/A TimeBuffer<RenameStruct> *renameQueue; 3521060SN/A 3531060SN/A /** Wire to read information from rename queue. */ 3541060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3551060SN/A 3562292SN/A public: 3571060SN/A /** ROB interface. */ 3581060SN/A ROB *rob; 3591060SN/A 3602292SN/A private: 3612733Sktlim@umich.edu /** Pointer to O3CPU. */ 3622733Sktlim@umich.edu O3CPU *cpu; 3631060SN/A 3642348SN/A /** Vector of all of the threads. */ 3652292SN/A std::vector<Thread *> thread; 3661060SN/A 3672292SN/A /** Records that commit has written to the time buffer this cycle. Used for 3682292SN/A * the CPU to determine if it can deschedule itself if there is no activity. 3692292SN/A */ 3702292SN/A bool wroteToTimeBuffer; 3712292SN/A 3722292SN/A /** Records if the number of ROB entries has changed this cycle. If it has, 3732292SN/A * then the number of free entries must be re-broadcast. 3742292SN/A */ 3752292SN/A bool changedROBNumEntries[Impl::MaxThreads]; 3762292SN/A 3772292SN/A /** Records if a thread has to squash this cycle due to a trap. */ 3782292SN/A bool trapSquash[Impl::MaxThreads]; 3792292SN/A 3802292SN/A /** Records if a thread has to squash this cycle due to an XC write. */ 3812680Sktlim@umich.edu bool tcSquash[Impl::MaxThreads]; 3822292SN/A 3839437SAndreas.Sandberg@ARM.com /** 3849437SAndreas.Sandberg@ARM.com * Instruction passed to squashAfter(). 3859437SAndreas.Sandberg@ARM.com * 3869437SAndreas.Sandberg@ARM.com * The squash after implementation needs to buffer the instruction 3879437SAndreas.Sandberg@ARM.com * that caused a squash since this needs to be passed to the fetch 3889437SAndreas.Sandberg@ARM.com * stage once squashing starts. 3899437SAndreas.Sandberg@ARM.com */ 3909437SAndreas.Sandberg@ARM.com DynInstPtr squashAfterInst[Impl::MaxThreads]; 3919437SAndreas.Sandberg@ARM.com 3922292SN/A /** Priority List used for Commit Policy */ 3936221Snate@binkert.org std::list<ThreadID> priority_list; 3942292SN/A 3959184Sandreas.hansson@arm.com /** IEW to Commit delay. */ 39610732Snilay@cs.wisc.edu const Cycles iewToCommitDelay; 3971060SN/A 3989184Sandreas.hansson@arm.com /** Commit to IEW delay. */ 39910732Snilay@cs.wisc.edu const Cycles commitToIEWDelay; 4002292SN/A 4019184Sandreas.hansson@arm.com /** Rename to ROB delay. */ 40210732Snilay@cs.wisc.edu const Cycles renameToROBDelay; 4031060SN/A 40410732Snilay@cs.wisc.edu const Cycles fetchToCommitDelay; 4052292SN/A 4061060SN/A /** Rename width, in instructions. Used so ROB knows how many 4071060SN/A * instructions to get from the rename instruction queue. 4081060SN/A */ 40910732Snilay@cs.wisc.edu const unsigned renameWidth; 4101060SN/A 4111060SN/A /** Commit width, in instructions. */ 41210732Snilay@cs.wisc.edu const unsigned commitWidth; 4131062SN/A 4142292SN/A /** Number of Reorder Buffers */ 4152292SN/A unsigned numRobs; 4162292SN/A 4172292SN/A /** Number of Active Threads */ 41810732Snilay@cs.wisc.edu const ThreadID numThreads; 4192292SN/A 42010340Smitch.hayenga@arm.com /** Is a drain pending? Commit is looking for an instruction boundary while 42110340Smitch.hayenga@arm.com * there are no pending interrupts 42210340Smitch.hayenga@arm.com */ 4232843Sktlim@umich.edu bool drainPending; 4242348SN/A 42510340Smitch.hayenga@arm.com /** Is a drain imminent? Commit has found an instruction boundary while no 42610340Smitch.hayenga@arm.com * interrupts were present or in flight. This was the last architecturally 42710340Smitch.hayenga@arm.com * committed instruction. Interrupts disabled and pipeline flushed. 42810340Smitch.hayenga@arm.com * Waiting for structures to finish draining. 42910340Smitch.hayenga@arm.com */ 43010340Smitch.hayenga@arm.com bool drainImminent; 43110340Smitch.hayenga@arm.com 4322348SN/A /** The latency to handle a trap. Used when scheduling trap 4332348SN/A * squash event. 4342348SN/A */ 43510732Snilay@cs.wisc.edu const Cycles trapLatency; 4362292SN/A 4373640Sktlim@umich.edu /** The interrupt fault. */ 4383640Sktlim@umich.edu Fault interrupt; 4393640Sktlim@umich.edu 4407720Sgblack@eecs.umich.edu /** The commit PC state of each thread. Refers to the instruction that 4412348SN/A * is currently being processed/committed. 4422348SN/A */ 4437720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4444636Sgblack@eecs.umich.edu 4452292SN/A /** The sequence number of the youngest valid instruction in the ROB. */ 4462292SN/A InstSeqNum youngestSeqNum[Impl::MaxThreads]; 4472292SN/A 4487855SAli.Saidi@ARM.com /** The sequence number of the last commited instruction. */ 4497855SAli.Saidi@ARM.com InstSeqNum lastCommitedSeqNum[Impl::MaxThreads]; 4507855SAli.Saidi@ARM.com 4514035Sktlim@umich.edu /** Records if there is a trap currently in flight. */ 4524035Sktlim@umich.edu bool trapInFlight[Impl::MaxThreads]; 4534035Sktlim@umich.edu 4544035Sktlim@umich.edu /** Records if there were any stores committed this cycle. */ 4554035Sktlim@umich.edu bool committedStores[Impl::MaxThreads]; 4564035Sktlim@umich.edu 4574035Sktlim@umich.edu /** Records if commit should check if the ROB is truly empty (see 4584035Sktlim@umich.edu commit_impl.hh). */ 4594035Sktlim@umich.edu bool checkEmptyROB[Impl::MaxThreads]; 4604035Sktlim@umich.edu 4612292SN/A /** Pointer to the list of active threads. */ 4626221Snate@binkert.org std::list<ThreadID> *activeThreads; 4632292SN/A 4642292SN/A /** Rename map interface. */ 4652292SN/A RenameMap *renameMap[Impl::MaxThreads]; 4662292SN/A 4678823Snilay@cs.wisc.edu /** True if last committed microop can be followed by an interrupt */ 4688823Snilay@cs.wisc.edu bool canHandleInterrupts; 4698823Snilay@cs.wisc.edu 4709513SAli.Saidi@ARM.com /** Have we had an interrupt pending and then seen it de-asserted because 4719513SAli.Saidi@ARM.com of a masking change? In this case the variable is set and the next time 4729513SAli.Saidi@ARM.com interrupts are enabled and pending the pipeline will squash to avoid 4739513SAli.Saidi@ARM.com a possible livelock senario. */ 4749513SAli.Saidi@ARM.com bool avoidQuiesceLiveLock; 4759513SAli.Saidi@ARM.com 4762348SN/A /** Updates commit stats based on this instruction. */ 47713429Srekai.gonzalezalberquilla@arm.com void updateComInstStats(const DynInstPtr &inst); 4782301SN/A 4792292SN/A /** Stat for the total number of squashed instructions discarded by commit. 4802292SN/A */ 4815999Snate@binkert.org Stats::Scalar commitSquashedInsts; 4822292SN/A /** Stat for the total number of times commit has had to stall due to a non- 4832292SN/A * speculative instruction reaching the head of the ROB. 4842292SN/A */ 4855999Snate@binkert.org Stats::Scalar commitNonSpecStalls; 4862292SN/A /** Stat for the total number of branch mispredicts that caused a squash. */ 4875999Snate@binkert.org Stats::Scalar branchMispredicts; 4882292SN/A /** Distribution of the number of committed instructions each cycle. */ 4895999Snate@binkert.org Stats::Distribution numCommittedDist; 4901062SN/A 4912316SN/A /** Total number of instructions committed. */ 4928834Satgutier@umich.edu Stats::Vector instsCommitted; 4938834Satgutier@umich.edu /** Total number of ops (including micro ops) committed. */ 4948834Satgutier@umich.edu Stats::Vector opsCommitted; 4952316SN/A /** Total number of software prefetches committed. */ 4965999Snate@binkert.org Stats::Vector statComSwp; 4972316SN/A /** Stat for the total number of committed memory references. */ 4985999Snate@binkert.org Stats::Vector statComRefs; 4992316SN/A /** Stat for the total number of committed loads. */ 5005999Snate@binkert.org Stats::Vector statComLoads; 50113652Sqtt2@cornell.edu /** Stat for the total number of committed atomics. */ 50213652Sqtt2@cornell.edu Stats::Vector statComAmos; 5032316SN/A /** Total number of committed memory barriers. */ 5045999Snate@binkert.org Stats::Vector statComMembars; 5052316SN/A /** Total number of committed branches. */ 5065999Snate@binkert.org Stats::Vector statComBranches; 50712110SRekai.GonzalezAlberquilla@arm.com /** Total number of vector instructions */ 50812110SRekai.GonzalezAlberquilla@arm.com Stats::Vector statComVector; 5097897Shestness@cs.utexas.edu /** Total number of floating point instructions */ 5107897Shestness@cs.utexas.edu Stats::Vector statComFloating; 5117897Shestness@cs.utexas.edu /** Total number of integer instructions */ 5127897Shestness@cs.utexas.edu Stats::Vector statComInteger; 5137897Shestness@cs.utexas.edu /** Total number of function calls */ 5147897Shestness@cs.utexas.edu Stats::Vector statComFunctionCalls; 51510193SCurtis.Dunham@arm.com /** Committed instructions by instruction type (OpClass) */ 51610193SCurtis.Dunham@arm.com Stats::Vector2d statCommittedInstType; 5172301SN/A 5182348SN/A /** Number of cycles where the commit bandwidth limit is reached. */ 5195999Snate@binkert.org Stats::Scalar commitEligibleSamples; 5201060SN/A}; 5211060SN/A 5222292SN/A#endif // __CPU_O3_COMMIT_HH__ 523