12SN/A/* 21458SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Gabe Black 302SN/A */ 312SN/A 321147SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 331147SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__ 342SN/A 352037SN/Anamespace LittleEndianGuest {} 362037SN/A 379329Sdam.sunwoo@arm.com#include "arch/alpha/ipr.hh" 382428SN/A#include "arch/alpha/types.hh" 396216Snate@binkert.org#include "base/types.hh" 408542Sgblack@eecs.umich.edu#include "cpu/static_inst_fwd.hh" 412SN/A 425569Snate@binkert.orgnamespace AlphaISA { 432238SN/A 445569Snate@binkert.orgusing namespace LittleEndianGuest; 452107SN/A 465569Snate@binkert.orgStaticInstPtr decodeInst(ExtMachInst); 475569Snate@binkert.org 485569Snate@binkert.orgconst Addr PageShift = 13; 495569Snate@binkert.orgconst Addr PageBytes = ULL(1) << PageShift; 505569Snate@binkert.orgconst Addr PageMask = ~(PageBytes - 1); 515569Snate@binkert.orgconst Addr PageOffset = PageBytes - 1; 525569Snate@binkert.org 535569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 545569Snate@binkert.org// 555569Snate@binkert.org// Translation stuff 565569Snate@binkert.org// 575569Snate@binkert.org 585569Snate@binkert.orgconst Addr PteShift = 3; 595569Snate@binkert.orgconst Addr NPtePageShift = PageShift - PteShift; 605569Snate@binkert.orgconst Addr NPtePage = ULL(1) << NPtePageShift; 615569Snate@binkert.orgconst Addr PteMask = NPtePage - 1; 625569Snate@binkert.org 635569Snate@binkert.org// User Virtual 645569Snate@binkert.orgconst Addr USegBase = ULL(0x0); 655569Snate@binkert.orgconst Addr USegEnd = ULL(0x000003ffffffffff); 665569Snate@binkert.org 675569Snate@binkert.org// Kernel Direct Mapped 685569Snate@binkert.orgconst Addr K0SegBase = ULL(0xfffffc0000000000); 695569Snate@binkert.orgconst Addr K0SegEnd = ULL(0xfffffdffffffffff); 705569Snate@binkert.org 715569Snate@binkert.org// Kernel Virtual 725569Snate@binkert.orgconst Addr K1SegBase = ULL(0xfffffe0000000000); 735569Snate@binkert.orgconst Addr K1SegEnd = ULL(0xffffffffffffffff); 745569Snate@binkert.org 755569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 765569Snate@binkert.org// 775569Snate@binkert.org// Interrupt levels 785569Snate@binkert.org// 795569Snate@binkert.orgenum InterruptLevels 805569Snate@binkert.org{ 815569Snate@binkert.org INTLEVEL_SOFTWARE_MIN = 4, 825569Snate@binkert.org INTLEVEL_SOFTWARE_MAX = 19, 835569Snate@binkert.org 845569Snate@binkert.org INTLEVEL_EXTERNAL_MIN = 20, 855569Snate@binkert.org INTLEVEL_EXTERNAL_MAX = 34, 865569Snate@binkert.org 875569Snate@binkert.org INTLEVEL_IRQ0 = 20, 885569Snate@binkert.org INTLEVEL_IRQ1 = 21, 895569Snate@binkert.org INTINDEX_ETHERNET = 0, 905569Snate@binkert.org INTINDEX_SCSI = 1, 915569Snate@binkert.org INTLEVEL_IRQ2 = 22, 925569Snate@binkert.org INTLEVEL_IRQ3 = 23, 935569Snate@binkert.org 945569Snate@binkert.org INTLEVEL_SERIAL = 33, 955569Snate@binkert.org 965569Snate@binkert.org NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 975569Snate@binkert.org}; 985569Snate@binkert.org 995569Snate@binkert.org// EV5 modes 1005569Snate@binkert.orgenum mode_type 1015569Snate@binkert.org{ 1025569Snate@binkert.org mode_kernel = 0, // kernel 1035569Snate@binkert.org mode_executive = 1, // executive (unused by unix) 1045569Snate@binkert.org mode_supervisor = 2, // supervisor (unused by unix) 1055569Snate@binkert.org mode_user = 3, // user mode 1065569Snate@binkert.org mode_number // number of modes 1075569Snate@binkert.org}; 1085569Snate@binkert.org 10910318Sandreas.hansson@arm.comconst int MachineBytes = 8; 1105569Snate@binkert.org 1116974Stjones1@inf.ed.ac.uk// Memory accesses cannot be unaligned 1126974Stjones1@inf.ed.ac.ukconst bool HasUnalignedMemAcc = false; 1136974Stjones1@inf.ed.ac.uk 1149329Sdam.sunwoo@arm.comconst bool CurThreadInfoImplemented = true; 1159329Sdam.sunwoo@arm.comconst int CurThreadInfoReg = AlphaISA::IPR_PALtemp23; 1169329Sdam.sunwoo@arm.com 1175569Snate@binkert.org} // namespace AlphaISA 1185569Snate@binkert.org 1191147SN/A#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 120