1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
33#define __ARCH_ALPHA_ISA_TRAITS_HH__
34
35namespace LittleEndianGuest {}
36
37#include "arch/alpha/ipr.hh"
38#include "arch/alpha/types.hh"
39#include "base/types.hh"
40#include "cpu/static_inst_fwd.hh"
41
42namespace AlphaISA {
43
44using namespace LittleEndianGuest;
45
46StaticInstPtr decodeInst(ExtMachInst);
47
48const Addr PageShift = 13;
49const Addr PageBytes = ULL(1) << PageShift;
50const Addr PageMask = ~(PageBytes - 1);
51const Addr PageOffset = PageBytes - 1;
52
53////////////////////////////////////////////////////////////////////////
54//
55//  Translation stuff
56//
57
58const Addr PteShift = 3;
59const Addr NPtePageShift = PageShift - PteShift;
60const Addr NPtePage = ULL(1) << NPtePageShift;
61const Addr PteMask = NPtePage - 1;
62
63// User Virtual
64const Addr USegBase = ULL(0x0);
65const Addr USegEnd = ULL(0x000003ffffffffff);
66
67// Kernel Direct Mapped
68const Addr K0SegBase = ULL(0xfffffc0000000000);
69const Addr K0SegEnd = ULL(0xfffffdffffffffff);
70
71// Kernel Virtual
72const Addr K1SegBase = ULL(0xfffffe0000000000);
73const Addr K1SegEnd = ULL(0xffffffffffffffff);
74
75////////////////////////////////////////////////////////////////////////
76//
77//  Interrupt levels
78//
79enum InterruptLevels
80{
81    INTLEVEL_SOFTWARE_MIN = 4,
82    INTLEVEL_SOFTWARE_MAX = 19,
83
84    INTLEVEL_EXTERNAL_MIN = 20,
85    INTLEVEL_EXTERNAL_MAX = 34,
86
87    INTLEVEL_IRQ0 = 20,
88    INTLEVEL_IRQ1 = 21,
89    INTINDEX_ETHERNET = 0,
90    INTINDEX_SCSI = 1,
91    INTLEVEL_IRQ2 = 22,
92    INTLEVEL_IRQ3 = 23,
93
94    INTLEVEL_SERIAL = 33,
95
96    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
97};
98
99// EV5 modes
100enum mode_type
101{
102    mode_kernel = 0,        // kernel
103    mode_executive = 1,     // executive (unused by unix)
104    mode_supervisor = 2,    // supervisor (unused by unix)
105    mode_user = 3,          // user mode
106    mode_number             // number of modes
107};
108
109const int MachineBytes = 8;
110
111// Memory accesses cannot be unaligned
112const bool HasUnalignedMemAcc = false;
113
114const bool CurThreadInfoImplemented = true;
115const int CurThreadInfoReg = AlphaISA::IPR_PALtemp23;
116
117} // namespace AlphaISA
118
119#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
120