1/*
2 * Copyright (c) 2016-2018,2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#include "cpu/o3/rename_map.hh"
45
46#include <vector>
47
48#include "cpu/reg_class.hh"
49#include "debug/Rename.hh"
50
51using namespace std;
52
53/**** SimpleRenameMap methods ****/
54
55SimpleRenameMap::SimpleRenameMap()
56    : freeList(NULL), zeroReg(IntRegClass,0)
57{
58}
59
60
61void
62SimpleRenameMap::init(unsigned size, SimpleFreeList *_freeList,
63                      RegIndex _zeroReg)
64{
65    assert(freeList == NULL);
66    assert(map.empty());
67
68    map.resize(size);
69    freeList = _freeList;
70    zeroReg = RegId(IntRegClass, _zeroReg);
71}
72
73SimpleRenameMap::RenameInfo
74SimpleRenameMap::rename(const RegId& arch_reg)
75{
76    PhysRegIdPtr renamed_reg;
77    // Record the current physical register that is renamed to the
78    // requested architected register.
79    PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
80
81    if (arch_reg == zeroReg) {
82        assert(prev_reg->isZeroReg());
83        renamed_reg = prev_reg;
84    } else if (prev_reg->getNumPinnedWrites() > 0) {
85        // Do not rename if the register is pinned
86        assert(arch_reg.getNumPinnedWrites() == 0);  // Prevent pinning the
87                                                     // same register twice
88        DPRINTF(Rename, "Renaming pinned reg, numPinnedWrites %d\n",
89                prev_reg->getNumPinnedWrites());
90        renamed_reg = prev_reg;
91        renamed_reg->decrNumPinnedWrites();
92    } else {
93        renamed_reg = freeList->getReg();
94        map[arch_reg.flatIndex()] = renamed_reg;
95        renamed_reg->setNumPinnedWrites(arch_reg.getNumPinnedWrites());
96        renamed_reg->setNumPinnedWritesToComplete(
97            arch_reg.getNumPinnedWrites() + 1);
98    }
99
100    DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was"
101            " %d (%d)\n",
102            arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
103            prev_reg->flatIndex(), prev_reg->flatIndex());
104
105    return RenameInfo(renamed_reg, prev_reg);
106}
107
108
109/**** UnifiedRenameMap methods ****/
110
111void
112UnifiedRenameMap::init(PhysRegFile *_regFile,
113                       RegIndex _intZeroReg,
114                       RegIndex _floatZeroReg,
115                       UnifiedFreeList *freeList,
116                       VecMode _mode)
117{
118    regFile = _regFile;
119    vecMode = _mode;
120
121    intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
122
123    floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
124
125    vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1);
126
127    vecElemMap.init(TheISA::NumVecRegs * NVecElems,
128            &(freeList->vecElemList), (RegIndex)-1);
129
130    predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1);
131
132    ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
133
134}
135
136void
137UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
138{
139    if (vecMode == Enums::Elem) {
140
141        /* The free list should currently be tracking full registers. */
142        panic_if(freeList->hasFreeVecElems(),
143                "The free list is already tracking Vec elems");
144        panic_if(freeList->numFreeVecRegs() !=
145                regFile->numVecPhysRegs() - TheISA::NumVecRegs,
146                "The free list has lost vector registers");
147
148        /* Split the free regs. */
149        while (freeList->hasFreeVecRegs()) {
150            auto vr = freeList->getVecReg();
151            auto range = this->regFile->getRegElemIds(vr);
152            freeList->addRegs(range.first, range.second);
153        }
154
155    } else if (vecMode == Enums::Full) {
156
157        /* The free list should currently be tracking register elems. */
158        panic_if(freeList->hasFreeVecRegs(),
159                "The free list is already tracking full Vec");
160        panic_if(freeList->numFreeVecElems() !=
161                 regFile->numVecElemPhysRegs() -
162                 TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg,
163                 "The free list has lost vector register elements");
164
165        auto range = regFile->getRegIds(VecRegClass);
166        freeList->addRegs(range.first + TheISA::NumVecRegs, range.second);
167
168        /* We remove the elems from the free list. */
169        while (freeList->hasFreeVecElems())
170            freeList->getVecElem();
171    }
172}
173
174void
175UnifiedRenameMap::switchMode(VecMode newVecMode)
176{
177    if (newVecMode == Enums::Elem && vecMode == Enums::Full) {
178
179        /* Switch to vector element rename mode. */
180        vecMode = Enums::Elem;
181
182        /* Split the mapping of each arch reg. */
183        int vec_idx = 0;
184        for (auto &vec: vecMap) {
185            PhysRegFile::IdRange range = this->regFile->getRegElemIds(vec);
186            auto idx = 0;
187            for (auto phys_elem = range.first;
188                 phys_elem < range.second; idx++, phys_elem++) {
189
190                setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem));
191            }
192            vec_idx++;
193        }
194
195    } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) {
196
197        /* Switch to full vector register rename mode. */
198        vecMode = Enums::Full;
199
200        /* To rebuild the arch regs we take the easy road:
201         *  1.- Stitch the elems together into vectors.
202         *  2.- Replace the contents of the register file with the vectors
203         *  3.- Set the remaining registers as free
204         */
205        TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
206        for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
207            VecReg dst = new_RF[i].as<TheISA::VecElem>();
208            for (uint32_t l = 0; l < NVecElems; l++) {
209                RegId s_rid(VecElemClass, i, l);
210                PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
211                dst[l] = regFile->readVecElem(s_prid);
212            }
213        }
214
215        for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
216            PhysRegId pregId(VecRegClass, i, 0);
217            regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]);
218        }
219
220    }
221}
222