14826Ssaidi@eecs.umich.edu/* 24826Ssaidi@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 34826Ssaidi@eecs.umich.edu * All rights reserved. 44826Ssaidi@eecs.umich.edu * 54826Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64826Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74826Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84826Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94826Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104826Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114826Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124826Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134826Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144826Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154826Ssaidi@eecs.umich.edu * 164826Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174826Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184826Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194826Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204826Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214826Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224826Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234826Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244826Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254826Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264826Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274826Ssaidi@eecs.umich.edu * 284826Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 294826Ssaidi@eecs.umich.edu * Ali Saidi 304826Ssaidi@eecs.umich.edu */ 314826Ssaidi@eecs.umich.edu 324826Ssaidi@eecs.umich.edu#include "arch/alpha/utility.hh" 3311793Sbrandon.potter@amd.com 344826Ssaidi@eecs.umich.edu#include "arch/alpha/vtophys.hh" 358706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 368780Sgblack@eecs.umich.edu#include "sim/full_system.hh" 374826Ssaidi@eecs.umich.edu 385569Snate@binkert.orgnamespace AlphaISA { 394826Ssaidi@eecs.umich.edu 405569Snate@binkert.orguint64_t 417707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 424826Ssaidi@eecs.umich.edu{ 438806Sgblack@eecs.umich.edu if (!FullSystem) { 448780Sgblack@eecs.umich.edu panic("getArgument() is Full system only\n"); 458780Sgblack@eecs.umich.edu M5_DUMMY_RETURN; 464826Ssaidi@eecs.umich.edu } 478806Sgblack@eecs.umich.edu 488806Sgblack@eecs.umich.edu const int NumArgumentRegs = 6; 498806Sgblack@eecs.umich.edu if (number < NumArgumentRegs) { 508806Sgblack@eecs.umich.edu if (fp) 5113611Sgabeblack@google.com return tc->readFloatReg(16 + number); 528806Sgblack@eecs.umich.edu else 538806Sgblack@eecs.umich.edu return tc->readIntReg(16 + number); 548806Sgblack@eecs.umich.edu } else { 558806Sgblack@eecs.umich.edu Addr sp = tc->readIntReg(StackPointerReg); 5614020Sgabeblack@google.com PortProxy &vp = tc->getVirtProxy(); 578852Sandreas.hansson@arm.com uint64_t arg = vp.read<uint64_t>(sp + 588852Sandreas.hansson@arm.com (number-NumArgumentRegs) * 598852Sandreas.hansson@arm.com sizeof(uint64_t)); 608806Sgblack@eecs.umich.edu return arg; 618806Sgblack@eecs.umich.edu } 624826Ssaidi@eecs.umich.edu} 634826Ssaidi@eecs.umich.edu 646329Sgblack@eecs.umich.eduvoid 656329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 666329Sgblack@eecs.umich.edu{ 676329Sgblack@eecs.umich.edu // First loop through the integer registers. 686329Sgblack@eecs.umich.edu for (int i = 0; i < NumIntRegs; ++i) 696329Sgblack@eecs.umich.edu dest->setIntReg(i, src->readIntReg(i)); 706329Sgblack@eecs.umich.edu 716329Sgblack@eecs.umich.edu // Then loop through the floating point registers. 726329Sgblack@eecs.umich.edu for (int i = 0; i < NumFloatRegs; ++i) 7313611Sgabeblack@google.com dest->setFloatReg(i, src->readFloatReg(i)); 746329Sgblack@eecs.umich.edu 759920Syasuko.eckert@amd.com // Would need to add condition-code regs if implemented 769920Syasuko.eckert@amd.com assert(NumCCRegs == 0); 779920Syasuko.eckert@amd.com 786329Sgblack@eecs.umich.edu // Copy misc. registers 796329Sgblack@eecs.umich.edu copyMiscRegs(src, dest); 806329Sgblack@eecs.umich.edu 816329Sgblack@eecs.umich.edu // Lastly copy PC/NPC 827720Sgblack@eecs.umich.edu dest->pcState(src->pcState()); 836329Sgblack@eecs.umich.edu} 846329Sgblack@eecs.umich.edu 856329Sgblack@eecs.umich.eduvoid 866329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 876329Sgblack@eecs.umich.edu{ 886329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FPCR, 896329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_FPCR)); 906329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_UNIQ, 916329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_UNIQ)); 926329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, 936329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); 946329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_LOCKADDR, 956329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_LOCKADDR)); 966329Sgblack@eecs.umich.edu 976329Sgblack@eecs.umich.edu copyIprs(src, dest); 986329Sgblack@eecs.umich.edu} 996329Sgblack@eecs.umich.edu 1007693SAli.Saidi@ARM.comvoid 1017693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 1027693SAli.Saidi@ARM.com{ 10313915Sgabeblack@google.com PCState newPC = tc->pcState(); 1047720Sgblack@eecs.umich.edu newPC.set(tc->readIntReg(ReturnAddressReg)); 1057720Sgblack@eecs.umich.edu tc->pcState(newPC); 1067693SAli.Saidi@ARM.com} 1077693SAli.Saidi@ARM.com 1087693SAli.Saidi@ARM.com 1094826Ssaidi@eecs.umich.edu} // namespace AlphaISA 1104826Ssaidi@eecs.umich.edu 111