| /gem5/tests/configs/ |
| H A D | t1000-simple-atomic.py | 44 cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) variable
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| H A D | simple-timing-ruby.py | 63 cpu = TimingSimpleCPU(cpu_id=0) variable
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| H A D | tgen-simple-mem.py | 48 cpu = TrafficGen( variable
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| H A D | tgen-dram-ctrl.py | 48 cpu = TrafficGen( variable
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| H A D | o3-timing-ruby.py | 35 cpu = DerivO3CPU(cpu_id=0) variable
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| /gem5/src/cpu/ |
| H A D | intr_control.cc | 54 BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); local
63 BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); local
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| H A D | thread_state.cc | 46 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) argument
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| H A D | base_dyn_inst_impl.hh | 62 BaseDynInst(const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop, TheISA::PCState _pc, TheISA::PCState _predPC, InstSeqNum seq_num, ImplCPU *cpu) argument
[all...] |
| H A D | thread_context.cc | 149 BaseCPU *cpu = getCpuPtr(); local
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| /gem5/src/dev/alpha/ |
| H A D | AlphaBackdoor.py | 38 cpu = Param.BaseCPU(Parent.cpu[0], "Processor") variable in class:AlphaBackdoor
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| H A D | backdoor.hh | 98 BaseCPU *cpu; member in class:AlphaBackdoor
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| /gem5/tests/gem5/memory/ |
| H A D | simple-run.py | 53 cpu = TrafficGen( variable
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| /gem5/src/cpu/o3/ |
| H A D | thread_context.hh | 76 O3CPU *cpu; member in class:O3ThreadContext
[all...] |
| H A D | thread_state.hh | 74 O3CPU *cpu; member in struct:O3ThreadState
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| H A D | dyn_inst_impl.hh | 52 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu) argument
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| /gem5/src/cpu/minor/ |
| H A D | decode.hh | 66 MinorCPU &cpu; member in class:Minor::Decode
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| H A D | cpu.hh | 104 MinorCPU &cpu; member in class:MinorCPU::MinorCPUPort
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| H A D | pipeline.hh | 74 MinorCPU &cpu; member in class:Minor::Pipeline
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| H A D | exec_context.hh | 77 MinorCPU &cpu; member in class:Minor::ExecContext
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| /gem5/src/mem/ruby/profiler/ |
| H A D | AccessTraceForAddress.cc | 62 update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu, bool sharing_miss) argument
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| /gem5/src/arch/power/ |
| H A D | interrupts.hh | 46 BaseCPU * cpu; member in class:PowerISA::Interrupts
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| /gem5/src/arch/sparc/ |
| H A D | ua2005.cc | 49 BaseCPU *cpu = tc->getCpuPtr(); local
94 BaseCPU *cpu local
329 BaseCPU *cpu = tc->getCpuPtr(); local
353 BaseCPU *cpu = tc->getCpuPtr(); local
[all...] |
| /gem5/src/arch/alpha/ |
| H A D | interrupts.hh | 55 BaseCPU * cpu; member in class:AlphaISA::Interrupts
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| H A D | ev5.cc | 85 zeroRegisters(CPU *cpu) argument
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| /gem5/src/sim/ |
| H A D | system.cc | 270 BaseCPU *cpu = tc->getCpuPtr(); local
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