1/*
2 * Copyright (c) 2011, 2019 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_BASE_DYN_INST_IMPL_HH__
44#define __CPU_BASE_DYN_INST_IMPL_HH__
45
46#include <iostream>
47#include <set>
48#include <sstream>
49#include <string>
50
51#include "base/cprintf.hh"
52#include "base/trace.hh"
53#include "config/the_isa.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/exetrace.hh"
56#include "debug/DynInst.hh"
57#include "debug/IQ.hh"
58#include "mem/request.hh"
59#include "sim/faults.hh"
60
61template <class Impl>
62BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
63                               const StaticInstPtr &_macroop,
64                               TheISA::PCState _pc, TheISA::PCState _predPC,
65                               InstSeqNum seq_num, ImplCPU *cpu)
66  : staticInst(_staticInst), cpu(cpu),
67    thread(nullptr),
68    traceData(nullptr),
69    macroop(_macroop),
70    memData(nullptr),
71    savedReq(nullptr),
72    reqToVerify(nullptr)
73{
74    seqNum = seq_num;
75
76    pc = _pc;
77    predPC = _predPC;
78
79    initVars();
80}
81
82template <class Impl>
83BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
84                               const StaticInstPtr &_macroop)
85    : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
86{
87    seqNum = 0;
88    initVars();
89}
90
91template <class Impl>
92void
93BaseDynInst<Impl>::initVars()
94{
95    memData = NULL;
96    effAddr = 0;
97    physEffAddr = 0;
98    readyRegs = 0;
99    memReqFlags = 0;
100
101    status.reset();
102
103    instFlags.reset();
104    instFlags[RecordResult] = true;
105    instFlags[Predicate] = true;
106    instFlags[MemAccPredicate] = true;
107
108    lqIdx = -1;
109    sqIdx = -1;
110
111    // Eventually make this a parameter.
112    threadNumber = 0;
113
114    // Also make this a parameter, or perhaps get it from xc or cpu.
115    asid = 0;
116
117    // Initialize the fault to be NoFault.
118    fault = NoFault;
119
120#ifndef NDEBUG
121    ++cpu->instcount;
122
123    if (cpu->instcount > 1500) {
124#ifdef DEBUG
125        cpu->dumpInsts();
126        dumpSNList();
127#endif
128        assert(cpu->instcount <= 1500);
129    }
130
131    DPRINTF(DynInst,
132        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
133        seqNum, cpu->name(), cpu->instcount);
134#endif
135
136#ifdef DEBUG
137    cpu->snList.insert(seqNum);
138#endif
139
140}
141
142template <class Impl>
143BaseDynInst<Impl>::~BaseDynInst()
144{
145    if (memData) {
146        delete [] memData;
147    }
148
149    if (traceData) {
150        delete traceData;
151    }
152
153    fault = NoFault;
154
155#ifndef NDEBUG
156    --cpu->instcount;
157
158    DPRINTF(DynInst,
159        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
160        seqNum, cpu->name(), cpu->instcount);
161#endif
162#ifdef DEBUG
163    cpu->snList.erase(seqNum);
164#endif
165
166}
167
168#ifdef DEBUG
169template <class Impl>
170void
171BaseDynInst<Impl>::dumpSNList()
172{
173    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
174
175    int count = 0;
176    while (sn_it != cpu->snList.end()) {
177        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
178        count++;
179        sn_it++;
180    }
181}
182#endif
183
184template <class Impl>
185void
186BaseDynInst<Impl>::dump()
187{
188    cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
189    std::cout << staticInst->disassemble(pc.instAddr());
190    cprintf("'\n");
191}
192
193template <class Impl>
194void
195BaseDynInst<Impl>::dump(std::string &outstring)
196{
197    std::ostringstream s;
198    s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
199      << staticInst->disassemble(pc.instAddr());
200
201    outstring = s.str();
202}
203
204template <class Impl>
205void
206BaseDynInst<Impl>::markSrcRegReady()
207{
208    DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
209            seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
210    if (++readyRegs == numSrcRegs()) {
211        setCanIssue();
212    }
213}
214
215template <class Impl>
216void
217BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
218{
219    _readySrcRegIdx[src_idx] = true;
220
221    markSrcRegReady();
222}
223
224template <class Impl>
225bool
226BaseDynInst<Impl>::eaSrcsReady() const
227{
228    // For now I am assuming that src registers 1..n-1 are the ones that the
229    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
230    // stored)
231
232    for (int i = 1; i < numSrcRegs(); ++i) {
233        if (!_readySrcRegIdx[i])
234            return false;
235    }
236
237    return true;
238}
239
240
241
242template <class Impl>
243void
244BaseDynInst<Impl>::setSquashed()
245{
246    status.set(Squashed);
247
248    if (!isPinnedRegsRenamed() || isPinnedRegsSquashDone())
249        return;
250
251    // This inst has been renamed already so it may go through rename
252    // again (e.g. if the squash is due to memory access order violation).
253    // Reset the write counters for all pinned destination register to ensure
254    // that they are in a consistent state for a possible re-rename. This also
255    // ensures that dest regs will be pinned to the same phys register if
256    // re-rename happens.
257    for (int idx = 0; idx < numDestRegs(); idx++) {
258        PhysRegIdPtr phys_dest_reg = renamedDestRegIdx(idx);
259        if (phys_dest_reg->isPinned()) {
260            phys_dest_reg->incrNumPinnedWrites();
261            if (isPinnedRegsWritten())
262                phys_dest_reg->incrNumPinnedWritesToComplete();
263        }
264    }
265    setPinnedRegsSquashDone();
266}
267
268
269
270#endif//__CPU_BASE_DYN_INST_IMPL_HH__
271