1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_THREAD_CONTEXT_HH__
45#define __CPU_O3_THREAD_CONTEXT_HH__
46
47#include "config/the_isa.hh"
48#include "cpu/o3/isa_specific.hh"
49#include "cpu/thread_context.hh"
50
51class EndQuiesceEvent;
52namespace Kernel {
53    class Statistics;
54}
55
56/**
57 * Derived ThreadContext class for use with the O3CPU.  It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state.  Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
68 */
69template <class Impl>
70class O3ThreadContext : public ThreadContext
71{
72  public:
73    typedef typename Impl::O3CPU O3CPU;
74
75   /** Pointer to the CPU. */
76    O3CPU *cpu;
77
78    /** Pointer to the thread state that this TC corrseponds to. */
79    O3ThreadState<Impl> *thread;
80
81    /** Returns a pointer to the ITB. */
82    BaseTLB *getITBPtr() override { return cpu->itb; }
83
84    /** Returns a pointer to the DTB. */
85    BaseTLB *getDTBPtr() override { return cpu->dtb; }
86
87    CheckerCPU *getCheckerCpuPtr() override { return NULL; }
88
89    TheISA::ISA *
90    getIsaPtr() override
91    {
92        return cpu->isa[thread->threadId()];
93    }
94
95    TheISA::Decoder *
96    getDecoderPtr() override
97    {
98        return cpu->fetch.decoder[thread->threadId()];
99    }
100
101    /** Returns a pointer to this CPU. */
102    BaseCPU *getCpuPtr() override { return cpu; }
103
104    /** Reads this CPU's ID. */
105    int cpuId() const override { return cpu->cpuId(); }
106
107    /** Reads this CPU's Socket ID. */
108    uint32_t socketId() const override { return cpu->socketId(); }
109
110    ContextID contextId() const override { return thread->contextId(); }
111
112    void setContextId(ContextID id) override { thread->setContextId(id); }
113
114    /** Returns this thread's ID number. */
115    int threadId() const override { return thread->threadId(); }
116    void setThreadId(int id) override { return thread->setThreadId(id); }
117
118    /** Returns a pointer to the system. */
119    System *getSystemPtr() override { return cpu->system; }
120
121    /** Returns a pointer to this thread's kernel statistics. */
122    ::Kernel::Statistics *
123    getKernelStats() override
124    {
125        return thread->kernelStats;
126    }
127
128    /** Returns a pointer to this thread's process. */
129    Process *getProcessPtr() override { return thread->getProcessPtr(); }
130
131    void setProcessPtr(Process *p) override { thread->setProcessPtr(p); }
132
133    PortProxy &getPhysProxy() override { return thread->getPhysProxy(); }
134
135    PortProxy &getVirtProxy() override;
136
137    void
138    initMemProxies(ThreadContext *tc) override
139    {
140        thread->initMemProxies(tc);
141    }
142
143    /** Returns this thread's status. */
144    Status status() const override { return thread->status(); }
145
146    /** Sets this thread's status. */
147    void
148    setStatus(Status new_status) override
149    {
150        thread->setStatus(new_status);
151    }
152
153    /** Set the status to Active. */
154    void activate() override;
155
156    /** Set the status to Suspended. */
157    void suspend() override;
158
159    /** Set the status to Halted. */
160    void halt() override;
161
162    /** Dumps the function profiling information.
163     * @todo: Implement.
164     */
165    void dumpFuncProfile() override;
166
167    /** Takes over execution of a thread from another CPU. */
168    void takeOverFrom(ThreadContext *old_context) override;
169
170    /** Registers statistics associated with this TC. */
171    void regStats(const std::string &name) override;
172
173    /** Reads the last tick that this thread was activated on. */
174    Tick readLastActivate() override;
175    /** Reads the last tick that this thread was suspended on. */
176    Tick readLastSuspend() override;
177
178    /** Clears the function profiling information. */
179    void profileClear() override;
180    /** Samples the function profiling information. */
181    void profileSample() override;
182
183    /** Copies the architectural registers from another TC into this TC. */
184    void copyArchRegs(ThreadContext *tc) override;
185
186    /** Resets all architectural registers to 0. */
187    void clearArchRegs() override;
188
189    /** Reads an integer register. */
190    RegVal
191    readReg(RegIndex reg_idx)
192    {
193        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
194                                                 reg_idx)).index());
195    }
196    RegVal
197    readIntReg(RegIndex reg_idx) const override
198    {
199        return readIntRegFlat(flattenRegId(RegId(IntRegClass,
200                                                 reg_idx)).index());
201    }
202
203    RegVal
204    readFloatReg(RegIndex reg_idx) const override
205    {
206        return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
207                                             reg_idx)).index());
208    }
209
210    const VecRegContainer &
211    readVecReg(const RegId& id) const override
212    {
213        return readVecRegFlat(flattenRegId(id).index());
214    }
215
216    /**
217     * Read vector register operand for modification, hierarchical indexing.
218     */
219    VecRegContainer &
220    getWritableVecReg(const RegId& id) override
221    {
222        return getWritableVecRegFlat(flattenRegId(id).index());
223    }
224
225    /** Vector Register Lane Interfaces. */
226    /** @{ */
227    /** Reads source vector 8bit operand. */
228    ConstVecLane8
229    readVec8BitLaneReg(const RegId& id) const override
230    {
231        return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
232                    id.elemIndex());
233    }
234
235    /** Reads source vector 16bit operand. */
236    ConstVecLane16
237    readVec16BitLaneReg(const RegId& id) const override
238    {
239        return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
240                    id.elemIndex());
241    }
242
243    /** Reads source vector 32bit operand. */
244    ConstVecLane32
245    readVec32BitLaneReg(const RegId& id) const override
246    {
247        return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
248                    id.elemIndex());
249    }
250
251    /** Reads source vector 64bit operand. */
252    ConstVecLane64
253    readVec64BitLaneReg(const RegId& id) const override
254    {
255        return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
256                    id.elemIndex());
257    }
258
259    /** Write a lane of the destination vector register. */
260    void
261    setVecLane(const RegId& reg,
262               const LaneData<LaneSize::Byte>& val) override
263    {
264        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
265    }
266    void
267    setVecLane(const RegId& reg,
268               const LaneData<LaneSize::TwoByte>& val) override
269    {
270        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
271    }
272    void
273    setVecLane(const RegId& reg,
274               const LaneData<LaneSize::FourByte>& val) override
275    {
276        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
277    }
278    void
279    setVecLane(const RegId& reg,
280               const LaneData<LaneSize::EightByte>& val) override
281    {
282        return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
283    }
284    /** @} */
285
286    const VecElem &
287    readVecElem(const RegId& reg) const override
288    {
289        return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
290    }
291
292    const VecPredRegContainer &
293    readVecPredReg(const RegId& id) const override
294    {
295        return readVecPredRegFlat(flattenRegId(id).index());
296    }
297
298    VecPredRegContainer&
299    getWritableVecPredReg(const RegId& id) override
300    {
301        return getWritableVecPredRegFlat(flattenRegId(id).index());
302    }
303
304    RegVal
305    readCCReg(RegIndex reg_idx) const override
306    {
307        return readCCRegFlat(flattenRegId(RegId(CCRegClass,
308                                                 reg_idx)).index());
309    }
310
311    /** Sets an integer register to a value. */
312    void
313    setIntReg(RegIndex reg_idx, RegVal val) override
314    {
315        setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
316    }
317
318    void
319    setFloatReg(RegIndex reg_idx, RegVal val) override
320    {
321        setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
322                                           reg_idx)).index(), val);
323    }
324
325    void
326    setVecReg(const RegId& reg, const VecRegContainer& val) override
327    {
328        setVecRegFlat(flattenRegId(reg).index(), val);
329    }
330
331    void
332    setVecElem(const RegId& reg, const VecElem& val) override
333    {
334        setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
335    }
336
337    void
338    setVecPredReg(const RegId& reg,
339                  const VecPredRegContainer& val) override
340    {
341        setVecPredRegFlat(flattenRegId(reg).index(), val);
342    }
343
344    void
345    setCCReg(RegIndex reg_idx, RegVal val) override
346    {
347        setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
348    }
349
350    /** Reads this thread's PC state. */
351    TheISA::PCState
352    pcState() const override
353    {
354        return cpu->pcState(thread->threadId());
355    }
356
357    /** Sets this thread's PC state. */
358    void pcState(const TheISA::PCState &val) override;
359
360    void pcStateNoRecord(const TheISA::PCState &val) override;
361
362    /** Reads this thread's PC. */
363    Addr
364    instAddr() const override
365    {
366        return cpu->instAddr(thread->threadId());
367    }
368
369    /** Reads this thread's next PC. */
370    Addr
371    nextInstAddr() const override
372    {
373        return cpu->nextInstAddr(thread->threadId());
374    }
375
376    /** Reads this thread's next PC. */
377    MicroPC
378    microPC() const override
379    {
380        return cpu->microPC(thread->threadId());
381    }
382
383    /** Reads a miscellaneous register. */
384    RegVal
385    readMiscRegNoEffect(RegIndex misc_reg) const override
386    {
387        return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
388    }
389
390    /** Reads a misc. register, including any side-effects the
391     * read might have as defined by the architecture. */
392    RegVal
393    readMiscReg(RegIndex misc_reg) override
394    {
395        return cpu->readMiscReg(misc_reg, thread->threadId());
396    }
397
398    /** Sets a misc. register. */
399    void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
400
401    /** Sets a misc. register, including any side-effects the
402     * write might have as defined by the architecture. */
403    void setMiscReg(RegIndex misc_reg, RegVal val) override;
404
405    RegId flattenRegId(const RegId& regId) const override;
406
407    /** Returns the number of consecutive store conditional failures. */
408    // @todo: Figure out where these store cond failures should go.
409    unsigned
410    readStCondFailures() const override
411    {
412        return thread->storeCondFailures;
413    }
414
415    /** Sets the number of consecutive store conditional failures. */
416    void
417    setStCondFailures(unsigned sc_failures) override
418    {
419        thread->storeCondFailures = sc_failures;
420    }
421
422    /** Executes a syscall in SE mode. */
423    void
424    syscall(int64_t callnum, Fault *fault) override
425    {
426        return cpu->syscall(callnum, thread->threadId(), fault);
427    }
428
429    /** Reads the funcExeInst counter. */
430    Counter readFuncExeInst() const override { return thread->funcExeInst; }
431
432    /** Returns pointer to the quiesce event. */
433    EndQuiesceEvent *
434    getQuiesceEvent() override
435    {
436        return this->thread->quiesceEvent;
437    }
438    /** check if the cpu is currently in state update mode and squash if not.
439     * This function will return true if a trap is pending or if a fault or
440     * similar is currently writing to the thread context and doesn't want
441     * reset all the state (see noSquashFromTC).
442     */
443    inline void
444    conditionalSquash()
445    {
446        if (!thread->trapPending && !thread->noSquashFromTC)
447            cpu->squashFromTC(thread->threadId());
448    }
449
450    RegVal readIntRegFlat(RegIndex idx) const override;
451    void setIntRegFlat(RegIndex idx, RegVal val) override;
452
453    RegVal readFloatRegFlat(RegIndex idx) const override;
454    void setFloatRegFlat(RegIndex idx, RegVal val) override;
455
456    const VecRegContainer& readVecRegFlat(RegIndex idx) const override;
457    /** Read vector register operand for modification, flat indexing. */
458    VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
459    void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override;
460
461    template <typename VecElem>
462    VecLaneT<VecElem, true>
463    readVecLaneFlat(RegIndex idx, int lId) const
464    {
465        return cpu->template readArchVecLane<VecElem>(idx, lId,
466                thread->threadId());
467    }
468
469    template <typename LD>
470    void
471    setVecLaneFlat(int idx, int lId, const LD& val)
472    {
473        cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
474    }
475
476    const VecElem &readVecElemFlat(RegIndex idx,
477                                   const ElemIndex& elemIndex) const override;
478    void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
479                        const VecElem& val) override;
480
481    const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override;
482    VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override;
483    void setVecPredRegFlat(RegIndex idx,
484                           const VecPredRegContainer& val) override;
485
486    RegVal readCCRegFlat(RegIndex idx) const override;
487    void setCCRegFlat(RegIndex idx, RegVal val) override;
488};
489
490#endif
491