12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Ron Dreslinski 302SN/A */ 312SN/A 3211793Sbrandon.potter@amd.com#include "cpu/intr_control.hh" 3311793Sbrandon.potter@amd.com 342SN/A#include <string> 352SN/A#include <vector> 362SN/A 375218Ssaidi@eecs.umich.edu#include "base/trace.hh" 381717SN/A#include "cpu/base.hh" 392680Sktlim@umich.edu#include "cpu/thread_context.hh" 408232Snate@binkert.org#include "debug/IntrControl.hh" 4156SN/A#include "sim/sim_object.hh" 422SN/A 432SN/Ausing namespace std; 442SN/A 455034Smilesck@eecs.umich.eduIntrControl::IntrControl(const Params *p) 465034Smilesck@eecs.umich.edu : SimObject(p), sys(p->sys) 472SN/A{} 482SN/A 49295SN/Avoid 50295SN/AIntrControl::post(int cpu_id, int int_num, int index) 51295SN/A{ 525218Ssaidi@eecs.umich.edu DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id); 534103Ssaidi@eecs.umich.edu std::vector<ThreadContext *> &tcvec = sys->threadContexts; 545218Ssaidi@eecs.umich.edu BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); 5511150Smitch.hayenga@arm.com cpu->postInterrupt(tcvec[cpu_id]->threadId(), int_num, index); 56295SN/A} 57295SN/A 58295SN/Avoid 59295SN/AIntrControl::clear(int cpu_id, int int_num, int index) 60295SN/A{ 615218Ssaidi@eecs.umich.edu DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id); 624103Ssaidi@eecs.umich.edu std::vector<ThreadContext *> &tcvec = sys->threadContexts; 635218Ssaidi@eecs.umich.edu BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); 6411150Smitch.hayenga@arm.com cpu->clearInterrupt(tcvec[cpu_id]->threadId(), int_num, index); 65295SN/A} 66295SN/A 674762Snate@binkert.orgIntrControl * 684762Snate@binkert.orgIntrControlParams::create() 692SN/A{ 705034Smilesck@eecs.umich.edu return new IntrControl(this); 712SN/A} 72