Searched refs:cpu (Results 1 - 25 of 194) sorted by relevance

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/gem5/tests/quick/se/00.hello/
H A Dtest.py29 root.system.cpu[0].workload = Process(cmd = 'hello',
31 if root.system.cpu[0].checker != NULL:
32 root.system.cpu[0].checker.workload = root.system.cpu[0].workload
/gem5/tests/quick/se/02.insttest/
H A Dtest.py29 root.system.cpu[0].workload = Process(cmd = 'insttest',
/gem5/tests/quick/se/00.hello.mp/
H A Dtest.py37 for i, cpu in zip(range(len(cpus)), root.system.cpu):
41 root.system.cpu[i].workload = p
42 root.system.cpu[i].max_insts_all_threads = 10000000
43 #root.system.cpu.workload = Process(cmd = 'hello',
/gem5/tests/configs/
H A Do3-timing-ruby.py35 cpu = DerivO3CPU(cpu_id=0) variable
37 system = System(cpu = cpu,
45 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
49 cpu.createInterruptController()
50 cpu.connectAllPorts(system.membus)
H A Do3-timing-mp-ruby.py39 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
47 for cpu in cpus:
49 cpu.createInterruptController()
50 cpu.connectAllPorts(system.membus)
52 cpu.clk_domain = system.cpu_clk_domain
H A Dsimple-atomic-mp-ruby.py39 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
44 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
47 for cpu in cpus:
48 cpu.connectAllPorts(system.membus)
50 cpu.clk_domain = system.cpu_clk_domain
H A Dt1000-simple-atomic.py44 cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) variable
45 system.cpu = cpu
47 cpu.createInterruptController()
48 cpu.connectAllPorts(system.membus)
H A Dmemtest.py39 system = System(cpu = cpus,
60 for cpu in cpus:
62 cpu.clk_domain = system.cpu_clk_domain
63 cpu.l1c = L1Cache(size = '32kB', assoc = 4)
64 cpu.l1c.cpu_side = cpu.port
65 cpu.l1c.mem_side = system.toL2Bus.slave
H A Dmemtest-filter.py39 system = System(cpu = cpus,
61 for cpu in cpus:
63 cpu.clk_domain = system.cpu_clk_domain
64 cpu.l1c = L1Cache(size = '32kB', assoc = 4)
65 cpu.l1c.cpu_side = cpu.port
66 cpu.l1c.mem_side = system.toL2Bus.slave
H A Dtgen-simple-mem.py46 # even if this is only a traffic generator, call it cpu to make sure
48 cpu = TrafficGen( variable
52 system = System(cpu = cpu, physmem = SimpleMemory(),
65 system.cpu.port = system.monitor.slave
/gem5/tests/gem5/cpu_tests/
H A Drun.py50 def connectCPU(self, cpu):
61 def connectCPU(self, cpu):
63 self.cpu_side = cpu.icache_port
71 def connectCPU(self, cpu):
73 self.cpu_side = cpu.dcache_port
115 parser.add_argument('--cpu', choices = valid_cpu.keys(),
128 if args.cpu != "AtomicSimpleCPU":
133 system.cpu = valid_cpu[args.cpu]()
135 if args.cpu
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/gem5/util/tlm/conf/
H A Dtlm_elastic_slave.py70 system = System(cpu=TraceCPU(cpu_id=0),
92 system.cpu.createInterruptController()
93 system.cpu.icache = L1_ICache(size="32kB")
94 system.cpu.dcache = L1_DCache(size="32kB")
95 system.cpu.icache.cpu_side = system.cpu.icache_port
96 system.cpu.dcache.cpu_side = system.cpu.dcache_port
99 system.cpu.instTraceFile="system.cpu
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/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py77 system = System(cpu=TraceCPU(cpu_id=0),
99 system.cpu.createInterruptController()
100 system.cpu.icache = L1_ICache(size="32kB")
101 system.cpu.dcache = L1_DCache(size="32kB")
102 system.cpu.icache.cpu_side = system.cpu.icache_port
103 system.cpu.dcache.cpu_side = system.cpu.dcache_port
106 system.cpu.instTraceFile="system.cpu
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/gem5/configs/learning_gem5/part3/
H A Dsimple_ruby.py69 system.cpu = [TimingSimpleCPU() for i in range(2)]
76 for cpu in system.cpu:
77 cpu.createInterruptController()
81 system.caches.setup(system, system.cpu, [system.mem_ctrl])
97 # Set the cpu to use the process as its workload and create thread contexts
98 for cpu in system.cpu:
99 cpu.workload = process
100 cpu
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/gem5/configs/learning_gem5/part1/
H A Dtwo_level.py96 system.cpu = TimingSimpleCPU()
99 system.cpu.icache = L1ICache(opts)
100 system.cpu.dcache = L1DCache(opts)
103 system.cpu.icache.connectCPU(system.cpu)
104 system.cpu.dcache.connectCPU(system.cpu)
110 system.cpu.icache.connectBus(system.l2bus)
111 system.cpu.dcache.connectBus(system.l2bus)
124 system.cpu
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H A Dsimple.py62 system.cpu = TimingSimpleCPU()
68 system.cpu.icache_port = system.membus.slave
69 system.cpu.dcache_port = system.membus.slave
72 system.cpu.createInterruptController()
77 system.cpu.interrupts[0].pio = system.membus.master
78 system.cpu.interrupts[0].int_master = system.membus.slave
79 system.cpu.interrupts[0].int_slave = system.membus.master
103 # Set the cpu to use the process as its workload and create thread contexts
104 system.cpu.workload = process
105 system.cpu
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/gem5/src/cpu/minor/
H A Dpipeline.cc40 #include "cpu/minor/pipeline.hh"
44 #include "cpu/minor/decode.hh"
45 #include "cpu/minor/execute.hh"
46 #include "cpu/minor/fetch1.hh"
47 #include "cpu/minor/fetch2.hh"
58 cpu(cpu_),
60 f1ToF2(cpu.name() + ".f1ToF2", "lines",
62 f2ToF1(cpu.name() + ".f2ToF1", "prediction",
64 f2ToD(cpu.name() + ".f2ToD", "insts",
66 dToE(cpu
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/gem5/tests/gem5/fs/linux/arm/
H A Drun.py76 if isinstance(system.cpu, list):
77 [ cpu.createThreads() for cpu in system.cpu ]
79 system.cpu.createThreads()
/gem5/src/arch/sparc/
H A Dua2005.cc35 #include "cpu/base.hh"
36 #include "cpu/thread_context.hh"
49 BaseCPU *cpu = tc->getCpuPtr(); local
53 cpu->postInterrupt(0, IT_SOFT_INT, 16);
55 cpu->clearInterrupt(0, IT_SOFT_INT, 16);
57 cpu->postInterrupt(0, IT_SOFT_INT, 0);
59 cpu->clearInterrupt(0, IT_SOFT_INT, 0);
64 cpu->postInterrupt(0, IT_SOFT_INT, bit);
66 cpu->clearInterrupt(0, IT_SOFT_INT, bit);
94 BaseCPU *cpu local
329 BaseCPU *cpu = tc->getCpuPtr(); local
353 BaseCPU *cpu = tc->getCpuPtr(); local
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/gem5/tests/gem5/memory/
H A Dmemtest-run.py40 system = System(cpu = cpus,
61 for cpu in cpus:
63 cpu.clk_domain = system.cpu_clk_domain
64 cpu.l1c = L1Cache(size = '32kB', assoc = 4)
65 cpu.l1c.cpu_side = cpu.port
66 cpu.l1c.mem_side = system.toL2Bus.slave
/gem5/tests/legacy-configs/
H A Drun.py92 def initCPU(cpu):
96 cpu.createThreads()
101 if not hasattr(sys, "cpu"):
105 if isinstance(sys.cpu, list):
106 [ initCPU(cpu) for cpu in sys.cpu ]
108 initCPU(sys.cpu)
111 # cpu[0].workload, although I think most legacy configs do this automatically
/gem5/configs/example/
H A Detrace_replay.py73 "--cpu-type=TraceCPU\n");
83 system = System(cpu = CPUClass(cpu_id=0),
107 for cpu in system.cpu:
108 cpu.clk_domain = system.cpu_clk_domain
111 # createThreads() is needed to fill in the cpu.isa
112 for cpu in system.cpu:
113 cpu.createThreads()
116 system.cpu
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/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py57 system.cpu = TimingSimpleCPU()
68 system.cpu.icache_port = system.cache.cpu_side
69 system.cpu.dcache_port = system.cache.cpu_side
75 system.cpu.createInterruptController()
76 system.cpu.interrupts[0].pio = system.membus.master
77 system.cpu.interrupts[0].int_master = system.membus.slave
78 system.cpu.interrupts[0].int_slave = system.membus.master
97 # Set the cpu to use the process as its workload and create thread contexts
98 system.cpu.workload = process
99 system.cpu
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H A Dsimple_memobj.py57 system.cpu = TimingSimpleCPU()
63 system.cpu.icache_port = system.memobj.inst_port
64 system.cpu.dcache_port = system.memobj.data_port
73 system.cpu.createInterruptController()
74 system.cpu.interrupts[0].pio = system.membus.master
75 system.cpu.interrupts[0].int_master = system.membus.slave
76 system.cpu.interrupts[0].int_slave = system.membus.master
95 # Set the cpu to use the process as its workload and create thread contexts
96 system.cpu.workload = process
97 system.cpu
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/gem5/src/arch/power/
H A Dinterrupts.hh46 BaseCPU * cpu; member in class:PowerISA::Interrupts
57 Interrupts(Params * p) : SimObject(p), cpu(NULL)
63 cpu = _cpu;

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