Lines Matching refs:cpu
50 def connectCPU(self, cpu):
61 def connectCPU(self, cpu):
63 self.cpu_side = cpu.icache_port
71 def connectCPU(self, cpu):
73 self.cpu_side = cpu.dcache_port
115 parser.add_argument('--cpu', choices = valid_cpu.keys(),
128 if args.cpu != "AtomicSimpleCPU":
133 system.cpu = valid_cpu[args.cpu]()
135 if args.cpu == "AtomicSimpleCPU":
137 system.cpu.icache_port = system.membus.slave
138 system.cpu.dcache_port = system.membus.slave
140 system.cpu.l1d = L1DCache()
141 system.cpu.l1i = L1ICache()
145 system.cpu.l1d.connectCPU(system.cpu)
146 system.cpu.l1d.connectBus(system.l1_to_l2)
147 system.cpu.l1i.connectCPU(system.cpu)
148 system.cpu.l1i.connectBus(system.l1_to_l2)
152 system.cpu.createInterruptController()
154 system.cpu.interrupts[0].pio = system.membus.master
155 system.cpu.interrupts[0].int_master = system.membus.slave
156 system.cpu.interrupts[0].int_slave = system.membus.master
165 system.cpu.workload = process
166 system.cpu.createThreads()