Searched refs:clock (Results 226 - 250 of 302) sorted by relevance

1234567891011>>

/gem5/tests/gem5/memory/
H A Dmemtest-run.py43 # Dummy voltage domain for all our clock domains
45 system.clk_domain = SrcClockDomain(clock = '1GHz',
48 # Create a seperate clock domain for components that should run at
50 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
/gem5/configs/splash2/
H A Dcluster.py175 cluster.clusterbus = L2XBar(clock=busFrequency)
178 clock=options.frequency) variable in class:Cluster
188 cluster.clusterbus = L2XBar(clock=busFrequency)
191 clock=options.frequency) variable
201 cluster.clusterbus = L2XBar(clock=busFrequency)
204 clock=options.frequency) variable
215 membus = SystemXBar(clock = busFrequency))
216 system.clock = '1GHz'
218 system.toL2bus = L2XBar(clock = busFrequency)
H A Drun.py185 clock=options.frequency) variable
189 clock=options.frequency) variable
193 clock=options.frequency) variable
200 membus = SystemXBar(clock = busFrequency))
201 system.clock = '1GHz'
203 system.toL2bus = L2XBar(clock = busFrequency)
/gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test6/
H A Dtest6.cpp40 Case 5: Checking multiple clock transitions at the same time
49 sc_in<bool> clock; local
59 clock(CLOCK);
61 sensitive << clock; local
/gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test7/
H A Dtest7.cpp40 Case 5: Checking multiple clock transitions at the same time
49 sc_in<bool> clock; local
59 clock(CLOCK);
61 sensitive << clock; local
/gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test8/
H A Dtest8.cpp49 Case 5: Checking multiple clock transitions at the same time
58 sc_in<bool> clock; local
68 clock(CLOCK);
70 sensitive << clock; local
/gem5/tests/configs/
H A Dpc-simple-timing-ruby.py58 # Dummy voltage domain for all our clock domains
62 system.clk_domain = SrcClockDomain(clock = '1GHz',
64 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
71 # Create a seperate clock domain for Ruby
72 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
H A Dtgen-simple-mem.py54 clk_domain = SrcClockDomain(clock = '1GHz',
H A Dtgen-dram-ctrl.py54 clk_domain = SrcClockDomain(clock = '1GHz',
H A Drubytest-ruby.py75 # We set the testers as cpu for ruby to find the correct clock domains
79 # Dummy voltage domain for all our clock domains
81 system.clk_domain = SrcClockDomain(clock = '1GHz',
88 # Create a separate clock domain for Ruby
89 system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
/gem5/util/tlm/conf/
H A Dtlm_master.py58 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
H A Dtlm_slave.py60 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
H A Dtlm_elastic_slave.py78 # Create a source clock for the system. This is used as the clock period for
80 system.clk_domain = SrcClockDomain(clock = '1GHz',
86 # Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
88 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
/gem5/src/systemc/tests/systemc/misc/sim_tests/popc/
H A Dpopc.cpp213 sc_clock clock("CLOCK", 10, SC_NS, 0.5, 0.0, SC_NS);
215 proc1 TestBench("TestBench", clock, data_ack, popc, reset, data_ready, in);
216 proc2 Popc("Popc", clock, reset, data_ready, in, data_ack, popc);
227 // sc_trace(tf, clock.signal(), "Clock");
228 sc_trace(tf, clock, "Clock");
/gem5/src/arch/mips/
H A DMipsSystem.py53 boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock[0]
/gem5/configs/learning_gem5/part3/
H A Druby_test.py50 # Set the clock fequency of the system (and all of its children)
52 system.clk_domain.clock = '1GHz'
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py85 # Create a source clock for the system. This is used as the clock period for
87 system.clk_domain = SrcClockDomain(clock = '1GHz',
93 # Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
95 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
/gem5/src/systemc/tests/systemc/kernel/dynamic_processes/test10/
H A Dtest10.cpp166 sc_clock clock; local
169 dut.m_clk(clock);
/gem5/configs/example/
H A Detrace_replay.py91 # Create a source clock for the system. This is used as the clock period for
93 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
99 # Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
101 system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
H A Druby_mem_test.py110 clk_domain = SrcClockDomain(clock = options.sys_clock),
130 # Create a top-level voltage domain and clock domain
132 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
134 # Create a seperate clock domain for Ruby
135 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
/gem5/src/gpu-compute/
H A Dgpu_tlb.hh74 // TLB clock: will inherit clock from shader's clock period in terms
75 // of nuber of ticks of curTime (aka global simulation clock)
76 // The assignment of TLB clock from shader clock is done in the python
78 int clock; member in class:X86ISA::GpuTLB
81 // clock related functions ; maps to-and-from Simulation ticks and
83 Tick frequency() const { return SimClock::Frequency / clock; }
88 return (Tick)clock * numCycle
[all...]
/gem5/src/systemc/channel/
H A Dsc_clock.cc56 ClockTick(::sc_core::sc_clock *clock, bool to, argument
59 _period(_period), name(clock->basename()), p(nullptr),
60 funcWrapper(clock, to ? &::sc_core::sc_clock::tickUp :
97 sc_clock(sc_gen_unique_name("clock"), sc_time(1.0, SC_NS),
114 "increase the period: clock '" +
121 "increase the period or increase the duty cycle: clock '" +
128 "increase the period or decrease the duty cycle: clock '" +
/gem5/src/systemc/tests/systemc/misc/communication/channel/hwsw/
H A Dhwsw.cpp174 sc_clock clock("Clock", 10, SC_NS, 0.5, 0, SC_NS, 0);
176 testbench T("TB", clock, sum, d, a, b, c);
177 adder_sub AS("AS", clock, a, b, c, d, sum);
/gem5/src/systemc/tests/systemc/examples/updown/
H A Dupdown.cpp91 sc_clock clock; local
103 up_down_0.clk(clock);
110 "clock", "up", "down", "data_in", "parity_out",
/gem5/src/systemc/tests/systemc/kernel/dynamic_processes/test09/
H A Dtest09.cpp191 sc_clock clock; local
195 dut.m_clk(clock);

Completed in 27 milliseconds

1234567891011>>