Searched defs:clk_domain (Results 1 - 13 of 13) sorted by relevance

/gem5/tests/configs/
H A Dtgen-simple-mem.py54 clk_domain = SrcClockDomain(clock = '1GHz', variable
H A Dtgen-dram-ctrl.py54 clk_domain = SrcClockDomain(clock = '1GHz', variable
H A Do3-timing-mp-ruby.py41 clk_domain = SrcClockDomain(clock = '1GHz')) variable
H A Dsimple-atomic-mp-ruby.py40 clk_domain = SrcClockDomain(clock = '1GHz')) variable
H A Do3-timing-ruby.py41 clk_domain = SrcClockDomain(clock = '1GHz')) variable
H A Dgpu-ruby.py174 clk_domain = SrcClockDomain( variable
/gem5/src/arch/x86/
H A DX86LocalApic.py63 clk_domain = DerivedClockDomain( variable in class:X86LocalApic
/gem5/src/sim/
H A DClockDomain.py80 clk_domain = Param.ClockDomain("Parent clock domain") variable in class:DerivedClockDomain
H A DClockedObject.py67 clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain") variable in class:ClockedObject
H A Dclocked_object.hh118 Clocked(ClockDomain &clk_domain) argument
/gem5/tests/gem5/memory/
H A Dsimple-run.py70 clk_domain = SrcClockDomain(clock = '1GHz', variable
/gem5/configs/example/
H A Druby_mem_test.py110 clk_domain = SrcClockDomain(clock = options.sys_clock), variable
H A Dapu_se.py204 clk_domain = SrcClockDomain( variable
317 clk_domain = SrcClockDomain( variable
334 clk_domain = SrcClockDomain( variable
343 clk_domain = SrcClockDomain( variable

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