/gem5/src/arch/mips/ |
H A D | locked_mem.hh | 78 handleLockedRead(XC *xc, const RequestPtr &req) argument 80 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf); 84 req->contextId(), req->getPaddr() & ~0xf); 95 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument 97 if (req->isUncacheable()) { 100 req->setExtraData(2); 106 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 109 req->setExtraData(0); 128 req [all...] |
H A D | tlb.hh | 107 static Fault checkCacheability(const RequestPtr &req); 116 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 118 const RequestPtr &req, ThreadContext *tc, 121 const RequestPtr &req, 125 Fault translateInst(const RequestPtr &req, ThreadContext *tc); 126 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
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/gem5/src/arch/riscv/ |
H A D | locked_mem.hh | 88 handleLockedRead(XC *xc, const RequestPtr &req) argument 92 locked_addr_stack.push(req->getPaddr() & ~0xF); 94 req->contextId(), req->getPaddr() & ~0xF); 102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument 111 DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(), 114 DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(), 115 req->getPaddr() & ~0xF); 116 DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(), 120 || locked_addr_stack.top() != ((req [all...] |
H A D | tlb.cc | 147 TLB::checkCacheability(const RequestPtr &req) 152 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 154 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 287 TLB::translateInst(const RequestPtr &req, ThreadContext *tc) 295 req->setFlags(Request::PHYSICAL); 297 if (req->getFlags() & Request::PHYSICAL) { 301 req->setPaddr(req->getVaddr()); 302 return checkCacheability(req); 313 Fault fault = p->pTable->translate(req); [all...] |
H A D | tlb.hh | 106 static Fault checkCacheability(const RequestPtr &req); 115 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 117 const RequestPtr &req, ThreadContext *tc, 120 const RequestPtr &req, 124 Fault translateInst(const RequestPtr &req, ThreadContext *tc); 125 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
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/gem5/src/arch/generic/ |
H A D | tlb.cc | 40 GenericTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode) argument 47 Fault fault = p->pTable->translate(req); 55 GenericTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, argument 59 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); local 63 GenericTLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc, argument
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H A D | tlb.hh | 78 virtual void finish(const Fault &fault, const RequestPtr &req, 93 const RequestPtr &req, ThreadContext *tc, Mode mode) = 0; 95 const RequestPtr &req, ThreadContext *tc, 98 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) argument 112 * @param req Request to updated in-place. 118 const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0; 155 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 157 const RequestPtr &req, ThreadContext *tc, 161 const RequestPtr &req, ThreadContext *tc, Mode mode) const override;
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H A D | locked_mem.hh | 66 handleLockedRead(XC *xc, const RequestPtr &req) argument 79 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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/gem5/src/sim/probe/ |
H A D | mem.hh | 66 flags(pkt->req->getFlags()), 67 pc(pkt->req->hasPC() ? pkt->req->getPC() : 0), 68 master(pkt->req->masterId()) { }
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/gem5/src/dev/arm/ |
H A D | amba.hh | 53 return pkt->req->masterId();
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/gem5/src/dev/virtio/ |
H A D | block.cc | 71 VirtIOBlock::read(const BlkRequest &req, VirtDescriptor *desc_chain, argument 75 uint64_t sector(req.sector); 97 VirtIOBlock::write(const BlkRequest &req, VirtDescriptor *desc_chain, argument 101 uint64_t sector(req.sector); 133 BlkRequest req; local 134 desc->chainRead(0, (uint8_t *)&req, sizeof(req)); 135 req.type = htov_legacy(req.type); 136 req [all...] |
/gem5/src/arch/alpha/ |
H A D | tlb.cc | 206 TLB::checkCacheability(const RequestPtr &req, bool itb) argument 221 if (req->getPaddr() & PAddrUncachedBit43) { 223 if (PAddrIprSpace(req->getPaddr())) { 228 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 232 req->setPaddr(req->getPaddr() & PAddrUncachedMask); 237 if (req->isUncacheable() && itb) 375 TLB::translateInst(const RequestPtr &req, ThreadContext *tc) argument 378 if (FullSystem && PcPAL(req->getPC())) 379 req 452 translateData(const RequestPtr &req, ThreadContext *tc, bool write) argument 602 translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) argument 611 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument 615 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); local 619 finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const argument [all...] |
H A D | locked_mem.hh | 88 handleLockedRead(XC *xc, const RequestPtr &req) argument 90 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument 104 if (req->isUncacheable()) { 107 req->setExtraData(2); 112 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 115 req->setExtraData(0);
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/gem5/src/mem/qos/ |
H A D | policy.cc | 53 assert(pkt->req); 54 return schedule(pkt->req->masterId(), pkt->getSize());
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/gem5/src/arch/arm/ |
H A D | stage2_mmu.cc | 70 auto req = std::make_shared<Request>(); local 71 req->setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0); 73 fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read); 75 fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read); 79 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 80 Packet pkt = Packet(req, MemCmd::ReadReq); 116 req = std::make_shared<Request>(); 121 const RequestPtr &req, 134 if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 136 MemCmd::ReadReq, req 120 finish(const Fault &_fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument [all...] |
H A D | stage2_lookup.hh | 71 RequestPtr req; member in class:ArmISA::Stage2LookUp 85 req = std::make_shared<Request>(); 86 req->setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(), 92 void mergeTe(const RequestPtr &req, BaseTLB::Mode mode); 100 void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
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H A D | vtophys.cc | 73 auto req = std::make_shared<Request>(0, addr, 64, 0x40, -1, 0, 0); local 84 fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran); 86 return std::make_pair(true, req->getPaddr()); 89 fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran); 91 return std::make_pair(true, req->getPaddr());
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/gem5/src/mem/cache/ |
H A D | cache_blk.hh | 141 bool matches(const RequestPtr &req) const 143 Addr req_low = req->getPaddr(); 144 Addr req_high = req_low + req->getSize() -1; 145 return (contextId == req->contextId()) && 150 bool intersects(const RequestPtr &req) const 152 Addr req_low = req->getPaddr(); 153 Addr req_high = req_low + req->getSize() - 1; 158 Lock(const RequestPtr &req) argument 159 : contextId(req->contextId()), 160 lowAddr(req 329 clearLoadLocks(const RequestPtr &req) argument 402 const RequestPtr &req = pkt->req; local [all...] |
/gem5/src/cpu/o3/ |
H A D | lsq_unit.hh | 101 LSQRequest* req; member in class:LSQUnit::LSQEntry 109 : inst(nullptr), req(nullptr), _size(0), _valid(false) 116 if (req != nullptr) { 117 req->freeLSQEntry(); 118 req = nullptr; 126 if (req != nullptr) { 127 req->freeLSQEntry(); 129 req = nullptr; 142 LSQRequest* request() { return req; } 143 void setRequest(LSQRequest* r) { req 613 read(LSQRequest *req, int load_idx) argument 855 write(LSQRequest *req, uint8_t *data, int store_idx) argument [all...] |
/gem5/src/cpu/testers/memtest/ |
H A D | memtest.cc | 137 const RequestPtr &req = pkt->req; local 138 assert(req->getSize() == 1); 141 auto remove_addr = outstandingAddrs.find(req->getPaddr()); 147 req->getPaddr(), blockAlign(req->getPaddr()), 155 pkt->isWrite() ? "Write" : "Read", req->getPaddr()); 159 uint8_t ref_data = referenceData[req->getPaddr()]; 163 req->getPaddr(), blockAlign(req [all...] |
/gem5/src/mem/ |
H A D | abstract_mem.hh | 84 bool matchesContext(const RequestPtr &req) const 87 assert(req->hasContextId()); 88 return (contextId == req->contextId()); 91 LockedAddr(const RequestPtr &req) : addr(mask(req->getPaddr())), argument 92 contextId(req->contextId()) 150 const RequestPtr &req = pkt->req; local 155 req->setExtraData(0);
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/gem5/ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_adapters/ |
H A D | tlm_adapters.h | 50 RSP transport( const REQ &req ) { 54 master_port->put( req ); 88 REQ req; local 93 slave_port->get( req ); 94 rsp = initiator_port->transport( req );
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | base_gen.cc | 65 RequestPtr req = std::make_shared<Request>(addr, size, flags, masterID); local 68 req->setPC(((Addr)masterID) << 2); 71 PacketPtr pkt = new Packet(req, cmd); 73 uint8_t* pkt_data = new uint8_t[req->getSize()]; 77 std::fill_n(pkt_data, req->getSize(), (uint8_t)masterID);
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/gem5/src/systemc/ext/tlm_core/1/req_rsp/adapters/ |
H A D | adapters.hh | 50 transport(const REQ &req) argument 53 master_port->put(req); 87 REQ req; local 91 slave_port->get(req); 92 rsp = initiator_port->transport(req);
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/gem5/src/arch/x86/ |
H A D | tlb.cc | 173 TLB::translateInt(const RequestPtr &req, ThreadContext *tc) argument 176 Addr vaddr = req->getVaddr(); 182 req->setFlags(Request::MMAPPED_IPR); 191 req->setPaddr((Addr)regNum * sizeof(RegVal)); 201 if (IOPort == 0xCF8 && req->getSize() == 4) { 202 req->setFlags(Request::MMAPPED_IPR); 203 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal)); 205 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 209 req->setPaddr(PhysAddrPrefixPciConfig | 213 req 227 finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const argument 269 translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing) argument 430 translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) argument 437 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument [all...] |