1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_GENERIC_TLB_HH__
44#define __ARCH_GENERIC_TLB_HH__
45
46#include "base/logging.hh"
47#include "mem/request.hh"
48#include "sim/sim_object.hh"
49
50class ThreadContext;
51
52class BaseTLB : public SimObject
53{
54  protected:
55    BaseTLB(const Params *p) : SimObject(p) {}
56
57  public:
58
59    enum Mode { Read, Write, Execute };
60
61    class Translation
62    {
63      public:
64        virtual ~Translation()
65        {}
66
67        /**
68         * Signal that the translation has been delayed due to a hw page table
69         * walk.
70         */
71        virtual void markDelayed() = 0;
72
73        /*
74         * The memory for this object may be dynamically allocated, and it may
75         * be responsible for cleaning itself up which will happen in this
76         * function. Once it's called, the object is no longer valid.
77         */
78        virtual void finish(const Fault &fault, const RequestPtr &req,
79                            ThreadContext *tc, Mode mode) = 0;
80
81        /** This function is used by the page table walker to determine if it
82         * should translate the a pending request or if the underlying request
83         * has been squashed.
84         * @ return Is the instruction that requested this translation squashed?
85         */
86        virtual bool squashed() const { return false; }
87    };
88
89  public:
90    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
91
92    virtual Fault translateAtomic(
93            const RequestPtr &req, ThreadContext *tc, Mode mode) = 0;
94    virtual void translateTiming(
95            const RequestPtr &req, ThreadContext *tc,
96            Translation *translation, Mode mode) = 0;
97    virtual Fault
98    translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
99    {
100        panic("Not implemented.\n");
101    }
102
103    /**
104     * Do post-translation physical address finalization.
105     *
106     * This method is used by some architectures that need
107     * post-translation massaging of physical addresses. For example,
108     * X86 uses this to remap physical addresses in the APIC range to
109     * a range of physical memory not normally available to real x86
110     * implementations.
111     *
112     * @param req Request to updated in-place.
113     * @param tc Thread context that created the request.
114     * @param mode Request type (read/write/execute).
115     * @return A fault on failure, NoFault otherwise.
116     */
117    virtual Fault finalizePhysical(
118            const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0;
119
120    /**
121     * Remove all entries from the TLB
122     */
123    virtual void flushAll() = 0;
124
125    /**
126     * Take over from an old tlb context
127     */
128    virtual void takeOverFrom(BaseTLB *otlb) = 0;
129
130    /**
131     * Get the table walker port if present. This is used for
132     * migrating port connections during a CPU takeOverFrom()
133     * call. For architectures that do not have a table walker, NULL
134     * is returned, hence the use of a pointer rather than a
135     * reference.
136     *
137     * @return A pointer to the walker port or NULL if not present
138     */
139    virtual Port* getTableWalkerPort() { return NULL; }
140
141    void memInvalidate() { flushAll(); }
142};
143
144class GenericTLB : public BaseTLB
145{
146  protected:
147    GenericTLB(const Params *p)
148        : BaseTLB(p)
149    {}
150
151  public:
152    void demapPage(Addr vaddr, uint64_t asn) override;
153
154    Fault translateAtomic(
155        const RequestPtr &req, ThreadContext *tc, Mode mode) override;
156    void translateTiming(
157        const RequestPtr &req, ThreadContext *tc,
158        Translation *translation, Mode mode) override;
159
160    Fault finalizePhysical(
161        const RequestPtr &req, ThreadContext *tc, Mode mode) const override;
162};
163
164#endif // __ARCH_GENERIC_TLB_HH__
165