1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__
44#define __ARCH_ALPHA_LOCKED_MEM_HH__
45
46/**
47 * @file
48 *
49 * ISA-specific helper functions for locked memory accesses.
50 *
51 * Note that these functions are not embedded in the ISA description
52 * because they operate on the *physical* address rather than the
53 * virtual address.  In the current M5 design, the physical address is
54 * not accessible from the ISA description, only from the CPU model.
55 * Thus the CPU is responsible for calling back to the ISA (here)
56 * after the address translation has been performed to allow the ISA
57 * to do these manipulations based on the physical address.
58 */
59
60#include "arch/alpha/registers.hh"
61#include "base/logging.hh"
62#include "mem/packet.hh"
63#include "mem/request.hh"
64
65namespace AlphaISA {
66
67template <class XC>
68inline void
69handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
70{
71    // If we see a snoop come into the CPU and we currently have an LLSC
72    // operation pending we need to clear the lock flag if it is to the same
73    // cache line.
74
75    if (!xc->readMiscReg(MISCREG_LOCKFLAG))
76        return;
77
78    Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
79    Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
80
81    if (locked_addr == snoop_addr)
82        xc->setMiscReg(MISCREG_LOCKFLAG, false);
83}
84
85
86template <class XC>
87inline void
88handleLockedRead(XC *xc, const RequestPtr &req)
89{
90    xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
91    xc->setMiscReg(MISCREG_LOCKFLAG, true);
92}
93
94template <class XC>
95inline void
96handleLockedSnoopHit(XC *xc)
97{
98}
99
100template <class XC>
101inline bool
102handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
103{
104    if (req->isUncacheable()) {
105        // Funky Turbolaser mailbox access...don't update
106        // result register (see stq_c in decoder.isa)
107        req->setExtraData(2);
108    } else {
109        // standard store conditional
110        bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
111        Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
112        if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
113            // Lock flag not set or addr mismatch in CPU;
114            // don't even bother sending to memory system
115            req->setExtraData(0);
116            xc->setMiscReg(MISCREG_LOCKFLAG, false);
117            // the rest of this code is not architectural;
118            // it's just a debugging aid to help detect
119            // livelock by warning on long sequences of failed
120            // store conditionals
121            int stCondFailures = xc->readStCondFailures();
122            stCondFailures++;
123            xc->setStCondFailures(stCondFailures);
124            if (stCondFailures % 100000 == 0) {
125                warn("context %d: %d consecutive "
126                     "store conditional failures\n",
127                     xc->contextId(), stCondFailures);
128            }
129
130            // store conditional failed already, so don't issue it to mem
131            return false;
132        }
133    }
134
135    return true;
136}
137
138template <class XC>
139inline void
140globalClearExclusive(XC *xc)
141{
142    xc->getCpuPtr()->wakeup(xc->threadId());
143}
144
145} // namespace AlphaISA
146
147#endif // __ARCH_ALPHA_LOCKED_MEM_HH__
148