14997SN/A/* 27944SN/A * Copyright (c) 2011 ARM Limited 37944SN/A * All rights reserved. 47944SN/A * 57944SN/A * The license below extends only to copyright in the software and shall 67944SN/A * not be construed as granting a license to any other intellectual 77944SN/A * property including but not limited to intellectual property relating 87944SN/A * to a hardware implementation of the functionality of the software 97944SN/A * licensed hereunder. You may use the software subject to the license 107944SN/A * terms below provided that you ensure that this notice is replicated 117944SN/A * unmodified and in its entirety in all distributions of the software, 127944SN/A * modified or unmodified, in source code or in binary form. 137944SN/A * 144997SN/A * Copyright (c) 2006 The Regents of The University of Michigan 154997SN/A * All rights reserved. 164997SN/A * 174997SN/A * Redistribution and use in source and binary forms, with or without 184997SN/A * modification, are permitted provided that the following conditions are 194997SN/A * met: redistributions of source code must retain the above copyright 204997SN/A * notice, this list of conditions and the following disclaimer; 214997SN/A * redistributions in binary form must reproduce the above copyright 224997SN/A * notice, this list of conditions and the following disclaimer in the 234997SN/A * documentation and/or other materials provided with the distribution; 244997SN/A * neither the name of the copyright holders nor the names of its 254997SN/A * contributors may be used to endorse or promote products derived from 264997SN/A * this software without specific prior written permission. 274997SN/A * 284997SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294997SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304997SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314997SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324997SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334997SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344997SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354997SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364997SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374997SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384997SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394997SN/A * 404997SN/A * Authors: Gabe Black 414997SN/A */ 424997SN/A 4310687SAndreas.Sandberg@ARM.com#ifndef __ARCH_GENERIC_TLB_HH__ 4410687SAndreas.Sandberg@ARM.com#define __ARCH_GENERIC_TLB_HH__ 454997SN/A 4612334Sgabeblack@google.com#include "base/logging.hh" 474997SN/A#include "mem/request.hh" 4813892Sgabeblack@google.com#include "sim/sim_object.hh" 494997SN/A 504997SN/Aclass ThreadContext; 514997SN/A 5213892Sgabeblack@google.comclass BaseTLB : public SimObject 535004SN/A{ 545004SN/A protected: 5513892Sgabeblack@google.com BaseTLB(const Params *p) : SimObject(p) {} 565004SN/A 574997SN/A public: 5813741SAndrea.Mondelli@ucf.edu 596023SN/A enum Mode { Read, Write, Execute }; 606023SN/A 615894SN/A class Translation 625894SN/A { 635894SN/A public: 645894SN/A virtual ~Translation() 655894SN/A {} 665894SN/A 677944SN/A /** 687944SN/A * Signal that the translation has been delayed due to a hw page table 697944SN/A * walk. 707944SN/A */ 717944SN/A virtual void markDelayed() = 0; 727944SN/A 735894SN/A /* 745894SN/A * The memory for this object may be dynamically allocated, and it may 755894SN/A * be responsible for cleaning itself up which will happen in this 765894SN/A * function. Once it's called, the object is no longer valid. 775894SN/A */ 7812749Sgiacomo.travaglini@arm.com virtual void finish(const Fault &fault, const RequestPtr &req, 7910379SN/A ThreadContext *tc, Mode mode) = 0; 809258SN/A 819258SN/A /** This function is used by the page table walker to determine if it 829258SN/A * should translate the a pending request or if the underlying request 839258SN/A * has been squashed. 849258SN/A * @ return Is the instruction that requested this translation squashed? 859258SN/A */ 869258SN/A virtual bool squashed() const { return false; } 875894SN/A }; 885358SN/A 895358SN/A public: 9012406Sgabeblack@google.com virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 915358SN/A 9212406Sgabeblack@google.com virtual Fault translateAtomic( 9312749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, Mode mode) = 0; 9412406Sgabeblack@google.com virtual void translateTiming( 9512749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, 9612406Sgabeblack@google.com Translation *translation, Mode mode) = 0; 9712406Sgabeblack@google.com virtual Fault 9812749Sgiacomo.travaglini@arm.com translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) 9912406Sgabeblack@google.com { 10012406Sgabeblack@google.com panic("Not implemented.\n"); 10112406Sgabeblack@google.com } 1029738SN/A 1039738SN/A /** 1049738SN/A * Do post-translation physical address finalization. 1059738SN/A * 1069738SN/A * This method is used by some architectures that need 1079738SN/A * post-translation massaging of physical addresses. For example, 1089738SN/A * X86 uses this to remap physical addresses in the APIC range to 1099738SN/A * a range of physical memory not normally available to real x86 1109738SN/A * implementations. 1119738SN/A * 1129738SN/A * @param req Request to updated in-place. 1139738SN/A * @param tc Thread context that created the request. 1149738SN/A * @param mode Request type (read/write/execute). 1159738SN/A * @return A fault on failure, NoFault otherwise. 1169738SN/A */ 11712406Sgabeblack@google.com virtual Fault finalizePhysical( 11812749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0; 11912406Sgabeblack@google.com 12012406Sgabeblack@google.com /** 12112406Sgabeblack@google.com * Remove all entries from the TLB 12212406Sgabeblack@google.com */ 12312406Sgabeblack@google.com virtual void flushAll() = 0; 12412406Sgabeblack@google.com 12512406Sgabeblack@google.com /** 12612406Sgabeblack@google.com * Take over from an old tlb context 12712406Sgabeblack@google.com */ 12812406Sgabeblack@google.com virtual void takeOverFrom(BaseTLB *otlb) = 0; 12912406Sgabeblack@google.com 13012406Sgabeblack@google.com /** 13113784Sgabeblack@google.com * Get the table walker port if present. This is used for 13212406Sgabeblack@google.com * migrating port connections during a CPU takeOverFrom() 13312406Sgabeblack@google.com * call. For architectures that do not have a table walker, NULL 13412406Sgabeblack@google.com * is returned, hence the use of a pointer rather than a 13512406Sgabeblack@google.com * reference. 13612406Sgabeblack@google.com * 13713784Sgabeblack@google.com * @return A pointer to the walker port or NULL if not present 13812406Sgabeblack@google.com */ 13913784Sgabeblack@google.com virtual Port* getTableWalkerPort() { return NULL; } 14012406Sgabeblack@google.com 14112406Sgabeblack@google.com void memInvalidate() { flushAll(); } 14212406Sgabeblack@google.com}; 14312406Sgabeblack@google.com 14412406Sgabeblack@google.comclass GenericTLB : public BaseTLB 14512406Sgabeblack@google.com{ 14612406Sgabeblack@google.com protected: 14712406Sgabeblack@google.com GenericTLB(const Params *p) 14812406Sgabeblack@google.com : BaseTLB(p) 14912406Sgabeblack@google.com {} 15012406Sgabeblack@google.com 15112406Sgabeblack@google.com public: 15212406Sgabeblack@google.com void demapPage(Addr vaddr, uint64_t asn) override; 15312406Sgabeblack@google.com 15412406Sgabeblack@google.com Fault translateAtomic( 15512749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, Mode mode) override; 15612406Sgabeblack@google.com void translateTiming( 15712749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, 15812406Sgabeblack@google.com Translation *translation, Mode mode) override; 15912406Sgabeblack@google.com 16012406Sgabeblack@google.com Fault finalizePhysical( 16112749Sgiacomo.travaglini@arm.com const RequestPtr &req, ThreadContext *tc, Mode mode) const override; 1624997SN/A}; 1634997SN/A 16410687SAndreas.Sandberg@ARM.com#endif // __ARCH_GENERIC_TLB_HH__ 165