112396SRiken.Gohil@arm.com/* 212811Sandreas.sandberg@arm.com * Copyright (c) 2012-2013, 2016-2018 ARM Limited 312396SRiken.Gohil@arm.com * All rights reserved 412396SRiken.Gohil@arm.com * 512396SRiken.Gohil@arm.com * The license below extends only to copyright in the software and shall 612396SRiken.Gohil@arm.com * not be construed as granting a license to any other intellectual 712396SRiken.Gohil@arm.com * property including but not limited to intellectual property relating 812396SRiken.Gohil@arm.com * to a hardware implementation of the functionality of the software 912396SRiken.Gohil@arm.com * licensed here under. You may use the software subject to the license 1012396SRiken.Gohil@arm.com * terms below provided that you ensure that this notice is replicated 1112396SRiken.Gohil@arm.com * unmodified and in its entirety in all distributions of the software, 1212396SRiken.Gohil@arm.com * modified or unmodified, in source code or in binary form. 1312396SRiken.Gohil@arm.com * 1412396SRiken.Gohil@arm.com * Redistribution and use in source and binary forms, with or without 1512396SRiken.Gohil@arm.com * modification, are permitted provided that the following conditions are 1612396SRiken.Gohil@arm.com * met: redistributions of source code must retain the above copyright 1712396SRiken.Gohil@arm.com * notice, this list of conditions and the following disclaimer; 1812396SRiken.Gohil@arm.com * redistributions in binary form must reproduce the above copyright 1912396SRiken.Gohil@arm.com * notice, this list of conditions and the following disclaimer in the 2012396SRiken.Gohil@arm.com * documentation and/or other materials provided with the distribution; 2112396SRiken.Gohil@arm.com * neither the name of the copyright holders nor the names of its 2212396SRiken.Gohil@arm.com * contributors may be used to endorse or promote products derived from 2312396SRiken.Gohil@arm.com * this software without specific prior written permission. 2412396SRiken.Gohil@arm.com * 2512396SRiken.Gohil@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612396SRiken.Gohil@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712396SRiken.Gohil@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812396SRiken.Gohil@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912396SRiken.Gohil@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012396SRiken.Gohil@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112396SRiken.Gohil@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212396SRiken.Gohil@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312396SRiken.Gohil@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412396SRiken.Gohil@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512396SRiken.Gohil@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612396SRiken.Gohil@arm.com * 3712396SRiken.Gohil@arm.com * Authors: Thomas Grass 3812396SRiken.Gohil@arm.com * Andreas Hansson 3912396SRiken.Gohil@arm.com * Sascha Bischoff 4012396SRiken.Gohil@arm.com * Neha Agarwal 4112396SRiken.Gohil@arm.com */ 4212396SRiken.Gohil@arm.com 4312396SRiken.Gohil@arm.com#include "cpu/testers/traffic_gen/base_gen.hh" 4412396SRiken.Gohil@arm.com 4512396SRiken.Gohil@arm.com#include <algorithm> 4612396SRiken.Gohil@arm.com 4712811Sandreas.sandberg@arm.com#include "base/logging.hh" 4812396SRiken.Gohil@arm.com#include "base/random.hh" 4912396SRiken.Gohil@arm.com#include "base/trace.hh" 5012811Sandreas.sandberg@arm.com#include "cpu/testers/traffic_gen/base.hh" 5112396SRiken.Gohil@arm.com#include "debug/TrafficGen.hh" 5212811Sandreas.sandberg@arm.com#include "sim/system.hh" 5312396SRiken.Gohil@arm.com 5412844Sgiacomo.travaglini@arm.comBaseGen::BaseGen(SimObject &obj, MasterID master_id, Tick _duration) 5512844Sgiacomo.travaglini@arm.com : _name(obj.name()), masterID(master_id), 5612811Sandreas.sandberg@arm.com duration(_duration) 5712396SRiken.Gohil@arm.com{ 5812396SRiken.Gohil@arm.com} 5912396SRiken.Gohil@arm.com 6012396SRiken.Gohil@arm.comPacketPtr 6112396SRiken.Gohil@arm.comBaseGen::getPacket(Addr addr, unsigned size, const MemCmd& cmd, 6212396SRiken.Gohil@arm.com Request::FlagsType flags) 6312396SRiken.Gohil@arm.com{ 6412396SRiken.Gohil@arm.com // Create new request 6512749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>(addr, size, flags, masterID); 6612396SRiken.Gohil@arm.com // Dummy PC to have PC-based prefetchers latch on; get entropy into higher 6712396SRiken.Gohil@arm.com // bits 6812396SRiken.Gohil@arm.com req->setPC(((Addr)masterID) << 2); 6912396SRiken.Gohil@arm.com 7012396SRiken.Gohil@arm.com // Embed it in a packet 7112396SRiken.Gohil@arm.com PacketPtr pkt = new Packet(req, cmd); 7212396SRiken.Gohil@arm.com 7312396SRiken.Gohil@arm.com uint8_t* pkt_data = new uint8_t[req->getSize()]; 7412396SRiken.Gohil@arm.com pkt->dataDynamic(pkt_data); 7512396SRiken.Gohil@arm.com 7612396SRiken.Gohil@arm.com if (cmd.isWrite()) { 7712396SRiken.Gohil@arm.com std::fill_n(pkt_data, req->getSize(), (uint8_t)masterID); 7812396SRiken.Gohil@arm.com } 7912396SRiken.Gohil@arm.com 8012396SRiken.Gohil@arm.com return pkt; 8112396SRiken.Gohil@arm.com} 8212811Sandreas.sandberg@arm.com 8312844Sgiacomo.travaglini@arm.comStochasticGen::StochasticGen(SimObject &obj, 8412844Sgiacomo.travaglini@arm.com MasterID master_id, Tick _duration, 8512844Sgiacomo.travaglini@arm.com Addr start_addr, Addr end_addr, 8612844Sgiacomo.travaglini@arm.com Addr _blocksize, Addr cacheline_size, 8712811Sandreas.sandberg@arm.com Tick min_period, Tick max_period, 8812811Sandreas.sandberg@arm.com uint8_t read_percent, Addr data_limit) 8912844Sgiacomo.travaglini@arm.com : BaseGen(obj, master_id, _duration), 9012811Sandreas.sandberg@arm.com startAddr(start_addr), endAddr(end_addr), 9112844Sgiacomo.travaglini@arm.com blocksize(_blocksize), cacheLineSize(cacheline_size), 9212844Sgiacomo.travaglini@arm.com minPeriod(min_period), maxPeriod(max_period), 9312844Sgiacomo.travaglini@arm.com readPercent(read_percent), dataLimit(data_limit) 9412811Sandreas.sandberg@arm.com{ 9512811Sandreas.sandberg@arm.com if (blocksize > cacheLineSize) 9612811Sandreas.sandberg@arm.com fatal("TrafficGen %s block size (%d) is larger than " 9712811Sandreas.sandberg@arm.com "cache line size (%d)\n", name(), 9812811Sandreas.sandberg@arm.com blocksize, cacheLineSize); 9912811Sandreas.sandberg@arm.com 10012811Sandreas.sandberg@arm.com if (read_percent > 100) 10112811Sandreas.sandberg@arm.com fatal("%s cannot have more than 100% reads", name()); 10212811Sandreas.sandberg@arm.com 10312811Sandreas.sandberg@arm.com if (min_period > max_period) 10412811Sandreas.sandberg@arm.com fatal("%s cannot have min_period > max_period", name()); 10512811Sandreas.sandberg@arm.com} 106