1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * Copyright (c) 2012 ARM Limited
6 * Copyright (c) 2014-2015 Sven Karlsson
7 * All rights reserved.
8 *
9 * The license below extends only to copyright in the software and shall
10 * not be construed as granting a license to any other intellectual
11 * property including but not limited to intellectual property relating
12 * to a hardware implementation of the functionality of the software
13 * licensed hereunder.  You may use the software subject to the license
14 * terms below provided that you ensure that this notice is replicated
15 * unmodified and in its entirety in all distributions of the software,
16 * modified or unmodified, in source code or in binary form.
17 *
18 * Copyright (c) 2006-2007 The Regents of The University of Michigan
19 * Copyright (c) 2016 The University of Virginia
20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are
24 * met: redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer;
26 * redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution;
29 * neither the name of the copyright holders nor the names of its
30 * contributors may be used to endorse or promote products derived from
31 * this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * Authors: Steve Reinhardt
46 *          Alec Roelke
47 */
48#ifndef __ARCH_RISCV_LOCKED_MEM_HH__
49#define __ARCH_RISCV_LOCKED_MEM_HH__
50
51#include <stack>
52#include <unordered_map>
53
54#include "arch/registers.hh"
55#include "base/logging.hh"
56#include "base/trace.hh"
57#include "debug/LLSC.hh"
58#include "mem/packet.hh"
59#include "mem/request.hh"
60
61/*
62 * ISA-specific helper functions for locked memory accesses.
63 */
64namespace RiscvISA
65{
66
67const int WARN_FAILURE = 10000;
68
69// RISC-V allows multiple locks per hart, but each SC has to unlock the most
70// recent one, so we use a stack here.
71extern std::unordered_map<int, std::stack<Addr>> locked_addrs;
72
73template <class XC> inline void
74handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
75{
76    std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
77
78    if (locked_addr_stack.empty())
79        return;
80    Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
81    DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
82    if ((locked_addr_stack.top() & cacheBlockMask) == snoop_addr)
83        locked_addr_stack.pop();
84}
85
86
87template <class XC> inline void
88handleLockedRead(XC *xc, const RequestPtr &req)
89{
90    std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
91
92    locked_addr_stack.push(req->getPaddr() & ~0xF);
93    DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
94            req->contextId(), req->getPaddr() & ~0xF);
95}
96
97template <class XC> inline void
98handleLockedSnoopHit(XC *xc)
99{}
100
101template <class XC> inline bool
102handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
103{
104    std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
105
106    // Normally RISC-V uses zero to indicate success and nonzero to indicate
107    // failure (right now only 1 is reserved), but in gem5 zero indicates
108    // failure and one indicates success, so here we conform to that (it should
109    // be switched in the instruction's implementation)
110
111    DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
112            locked_addr_stack.empty() ? "yes" : "no");
113    if (!locked_addr_stack.empty()) {
114        DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
115                req->getPaddr() & ~0xF);
116        DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
117                locked_addr_stack.top());
118    }
119    if (locked_addr_stack.empty()
120            || locked_addr_stack.top() != ((req->getPaddr() & ~0xF))) {
121        req->setExtraData(0);
122        int stCondFailures = xc->readStCondFailures();
123        xc->setStCondFailures(++stCondFailures);
124        if (stCondFailures % WARN_FAILURE == 0) {
125            warn("%i: context %d: %d consecutive SC failures.\n",
126                    curTick(), xc->contextId(), stCondFailures);
127        }
128        return false;
129    }
130    if (req->isUncacheable()) {
131        req->setExtraData(2);
132    }
133    return true;
134}
135
136template <class XC>
137inline void
138globalClearExclusive(XC *xc)
139{
140    xc->getCpuPtr()->wakeup(xc->threadId());
141}
142
143} // namespace RiscvISA
144
145#endif // __ARCH_RISCV_LOCKED_MEM_HH__
146