Searched refs:mem_side (Results 1 - 22 of 22) sorted by relevance

/gem5/src/learning_gem5/part2/
H A DSimpleMemobj.py39 mem_side = MasterPort("Memory side port, sends requests") variable in class:SimpleMemobj
H A DSimpleCache.py41 mem_side = MasterPort("Memory side port, sends requests") variable in class:SimpleCache
/gem5/src/mem/
H A DMemChecker.py54 mem_side = MasterPort("Alias for master") variable in class:MemCheckerMonitor
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py123 system.cpu.icache.mem_side = system.tol2bus.slave
124 system.cpu.dcache.mem_side = system.tol2bus.slave
126 system.l2cache.mem_side = system.membus.slave
/gem5/tests/configs/
H A Dmemtest.py57 system.l2c.mem_side = system.membus.slave
65 cpu.l1c.mem_side = system.toL2Bus.slave
H A Dmemtest-filter.py58 system.l2c.mem_side = system.membus.slave
66 cpu.l1c.mem_side = system.toL2Bus.slave
H A Dbase_config.py118 system.l2c.mem_side = system.membus.slave
292 system.physmem[i].port = system.llc[i].mem_side
298 system.iocache.mem_side = system.membus.slave
/gem5/tests/gem5/memory/
H A Dmemtest-run.py58 system.l2c.mem_side = system.membus.slave
66 cpu.l1c.mem_side = system.toL2Bus.slave
/gem5/util/tlm/conf/
H A Dtlm_elastic_slave.py115 system.cpu.icache.mem_side = system.membus.slave
116 system.cpu.dcache.mem_side = system.membus.slave
/gem5/configs/learning_gem5/part1/
H A Dcaches.py67 self.mem_side = bus.slave
136 self.mem_side = bus.slave
/gem5/tests/gem5/cpu_tests/
H A Drun.py48 self.mem_side = bus.slave
91 self.mem_side = bus.slave
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py72 system.cache.mem_side = system.membus.slave
H A Dsimple_memobj.py70 system.memobj.mem_side = system.membus.slave
/gem5/src/mem/cache/
H A DCache.py114 mem_side = MasterPort("Downstream port closer to memory") variable in class:BaseCache
/gem5/configs/example/
H A Dmemtest.py281 cache.mem_side = xbar.slave
285 cache.mem_side = xbar.slave
315 system.llc.mem_side = system.physmem.port
H A Dmemcheck.py273 cache.mem_side = xbar.slave
278 cache.mem_side = xbar.slave
H A Dfs.py188 test_sys.iocache.mem_side = test_sys.membus.slave
/gem5/configs/dram/
H A Dlat_mem_rd.py285 system.l1cache.mem_side = system.l2cache.xbar.slave
292 system.l2cache.mem_side = system.l3cache.xbar.slave
294 system.l3cache.mem_side = system.membus.slave
/gem5/configs/example/arm/
H A Ddevices.py164 self.l2.mem_side = bus.slave
240 self.iocache.mem_side = self.membus.slave
284 self.l3.mem_side = self.membus.slave
/gem5/configs/common/
H A DCacheConfig.py107 system.l2.mem_side = system.membus.slave
146 dcache_mon.mem_side = dcache.cpu_side
175 # The mem_side ports of the caches haven't been connected yet.
/gem5/configs/splash2/
H A Dcluster.py227 system.l2.mem_side = system.membus.master
234 cluster.l1.mem_side = system.toL2bus.slave
H A Drun.py212 system.l2.mem_side = system.membus.slave

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