| /gem5/src/cpu/simple/ |
| H A D | BaseSimpleCPU.py | 48 self.checker.itb = ArmTLB(size = self.itb.size)
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| H A D | base.cc | 100 p->itb, p->dtb, p->isa[i]);
103 p->itb, p->dtb, p->isa[i]);
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| /gem5/src/arch/sparc/ |
| H A D | tlb.cc | 870 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); local
907 pkt->setBE(itb->c0_tsb_ps0);
911 pkt->setBE(itb->c0_tsb_ps1);
915 pkt->setBE(itb->c0_config);
931 pkt->setBE(itb->cx_tsb_ps0);
935 pkt->setBE(itb->cx_tsb_ps1);
939 pkt->setBE(itb->cx_config);
951 temp = itb->tag_access;
955 pkt->setBE(itb->sfsr);
958 pkt->setBE(itb
1066 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); local
1303 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); local
[all...] |
| H A D | vtophys.cc | 86 TLB* itb = dynamic_cast<TLB *>(tc->getITBPtr()); local
105 tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context,
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| /gem5/src/arch/arm/ |
| H A D | ArmPMU.py | 103 itb=None, dtb=None,
124 self.addEvent(ProbeEvent(self,0x02, itb, "Refills"))
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| H A D | ArmTLB.py | 91 # We rely on the itb being a parameter of the CPU, and get the
93 tlb = Parent.itb
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| /gem5/src/cpu/checker/ |
| H A D | cpu.cc | 87 itb = p->itb;
106 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
111 itb, dtb, p->isa[0]);
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| H A D | cpu.hh | 137 BaseTLB *itb; member in class:CheckerCPU
160 BaseTLB* getITBPtr() { return itb; }
512 this->itb->demapPage(vaddr, asn);
527 this->itb->demapPage(vaddr, asn);
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| /gem5/src/cpu/o3/ |
| H A D | O3CPU.py | 190 self.checker.itb = ArmTLB(size = self.itb.size)
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| H A D | cpu.hh | 127 BaseTLB *itb; member in class:FullO3CPU
202 this->itb->demapPage(vaddr, asn);
208 this->itb->demapPage(vaddr, asn);
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| H A D | thread_context.hh | 82 BaseTLB *getITBPtr() override { return cpu->itb; }
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| /gem5/src/cpu/ |
| H A D | simple_thread.cc | 81 itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
92 itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
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| H A D | simple_thread.hh | 131 BaseTLB *itb; member in class:SimpleThread
171 itb->demapPage(vaddr, asn);
177 itb->demapPage(vaddr, asn);
200 BaseTLB *getITBPtr() override { return itb; }
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| H A D | BaseCPU.py | 184 itb = Param.BaseTLB(ArchITB(), "Instruction TLB") variable in class:BaseCPU
217 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
255 self.itb.walker.port = iwc.cpu_side
260 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
265 self._cached_ports += ["checker.itb.walker.port", \
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| /gem5/src/arch/alpha/ |
| H A D | tlb.hh | 117 static Fault checkCacheability(const RequestPtr &req, bool itb = false);
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| H A D | tlb.cc | 206 TLB::checkCacheability(const RequestPtr &req, bool itb) argument
237 if (req->isUncacheable() && itb)
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| /gem5/tests/configs/ |
| H A D | pc-simple-timing-ruby.py | 85 cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
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| /gem5/src/cpu/minor/ |
| H A D | cpu.cc | 60 params->itb, params->dtb, params->isa[i]);
64 params->workload[i], params->itb, params->dtb,
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| H A D | fetch1.cc | 189 cpu.threads[request->id.threadId]->itb->translateTiming(
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| /gem5/configs/learning_gem5/part3/ |
| H A D | msi_caches.py | 118 cpu.itb.walker.port = self.sequencers[i].slave
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| H A D | ruby_caches_MI_example.py | 116 cpu.itb.walker.port = self.sequencers[i].slave
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| /gem5/configs/example/ |
| H A D | se.py | 270 system.cpu[i].itb.walker.port = ruby_port.slave
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| H A D | fs.py | 175 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
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| H A D | apu_se.py | 468 system.cpu[i].itb.walker.port = ruby_port.slave
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| /gem5/src/cpu/kvm/ |
| H A D | base.cc | 89 thread = new SimpleThread(this, 0, params->system, params->itb, params->dtb,
93 params->workload[0], params->itb,
|