112276Sanouk.vanlaer@arm.com# Copyright (c) 2012-2013, 2015-2017 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 4312470Sglenn.bergmans@arm.com# Glenn Bergmans 444486Sbinkertn@umich.edu 4512563Sgabeblack@google.comfrom __future__ import print_function 4612563Sgabeblack@google.com 476654Snate@binkert.orgimport sys 486654Snate@binkert.org 4911988Sandreas.sandberg@arm.comfrom m5.SimObject import * 506654Snate@binkert.orgfrom m5.defines import buildEnv 513102SN/Afrom m5.params import * 523102SN/Afrom m5.proxy import * 5312470Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 546654Snate@binkert.org 5513892Sgabeblack@google.comfrom m5.objects.ClockedObject import ClockedObject 5613665Sandreas.sandberg@arm.comfrom m5.objects.XBar import L2XBar 5713665Sandreas.sandberg@arm.comfrom m5.objects.InstTracer import InstTracer 5813665Sandreas.sandberg@arm.comfrom m5.objects.CPUTracers import ExeTracer 5913665Sandreas.sandberg@arm.comfrom m5.objects.SubSystem import SubSystem 6013665Sandreas.sandberg@arm.comfrom m5.objects.ClockDomain import * 6113665Sandreas.sandberg@arm.comfrom m5.objects.Platform import Platform 622667SN/A 634776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 644776Sgblack@eecs.umich.edu 656654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 6613665Sandreas.sandberg@arm.com from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB 6714147Sgabeblack@google.com from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts 6814147Sgabeblack@google.com from m5.objects.AlphaISA import AlphaISA as ArchISA 6914147Sgabeblack@google.com ArchInterruptsParam = VectorParam.AlphaInterrupts 7014147Sgabeblack@google.com ArchISAsParam = VectorParam.AlphaISA 716654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 7213665Sandreas.sandberg@arm.com from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB 7314147Sgabeblack@google.com from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts 7414147Sgabeblack@google.com from m5.objects.SparcISA import SparcISA as ArchISA 7514147Sgabeblack@google.com ArchInterruptsParam = VectorParam.SparcInterrupts 7614147Sgabeblack@google.com ArchISAsParam = VectorParam.SparcISA 776654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 7813665Sandreas.sandberg@arm.com from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB 7914147Sgabeblack@google.com from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts 8014147Sgabeblack@google.com from m5.objects.X86ISA import X86ISA as ArchISA 8114147Sgabeblack@google.com ArchInterruptsParam = VectorParam.X86LocalApic 8214147Sgabeblack@google.com ArchISAsParam = VectorParam.X86ISA 836654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 8413665Sandreas.sandberg@arm.com from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB 8514147Sgabeblack@google.com from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts 8614147Sgabeblack@google.com from m5.objects.MipsISA import MipsISA as ArchISA 8714147Sgabeblack@google.com ArchInterruptsParam = VectorParam.MipsInterrupts 8814147Sgabeblack@google.com ArchISAsParam = VectorParam.MipsISA 896654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 9013665Sandreas.sandberg@arm.com from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB 9113665Sandreas.sandberg@arm.com from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU 9214147Sgabeblack@google.com from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts 9314147Sgabeblack@google.com from m5.objects.ArmISA import ArmISA as ArchISA 9414147Sgabeblack@google.com ArchInterruptsParam = VectorParam.ArmInterrupts 9514147Sgabeblack@google.com ArchISAsParam = VectorParam.ArmISA 966691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 9713665Sandreas.sandberg@arm.com from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB 9814147Sgabeblack@google.com from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts 9914147Sgabeblack@google.com from m5.objects.PowerISA import PowerISA as ArchISA 10014147Sgabeblack@google.com ArchInterruptsParam = VectorParam.PowerInterrupts 10114147Sgabeblack@google.com ArchISAsParam = VectorParam.PowerISA 10211723Sar4jc@virginia.eduelif buildEnv['TARGET_ISA'] == 'riscv': 10313665Sandreas.sandberg@arm.com from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB 10414147Sgabeblack@google.com from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts 10514147Sgabeblack@google.com from m5.objects.RiscvISA import RiscvISA as ArchISA 10614147Sgabeblack@google.com ArchInterruptsParam = VectorParam.RiscvInterrupts 10714147Sgabeblack@google.com ArchISAsParam = VectorParam.RiscvISA 10814147Sgabeblack@google.comelse: 10914147Sgabeblack@google.com print("Don't know what object types to use for ISA %s" % 11014147Sgabeblack@google.com buildEnv['TARGET_ISA']) 11114147Sgabeblack@google.com sys.exit(1) 1124486Sbinkertn@umich.edu 11313892Sgabeblack@google.comclass BaseCPU(ClockedObject): 1141366SN/A type = 'BaseCPU' 1151310SN/A abstract = True 1169338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 1179254SAndreas.Sandberg@arm.com 11811988Sandreas.sandberg@arm.com cxx_exports = [ 11911988Sandreas.sandberg@arm.com PyBindMethod("switchOut"), 12011988Sandreas.sandberg@arm.com PyBindMethod("takeOverFrom"), 12111988Sandreas.sandberg@arm.com PyBindMethod("switchedOut"), 12211988Sandreas.sandberg@arm.com PyBindMethod("flushTLBs"), 12311988Sandreas.sandberg@arm.com PyBindMethod("totalInsts"), 12411988Sandreas.sandberg@arm.com PyBindMethod("scheduleInstStop"), 12511988Sandreas.sandberg@arm.com PyBindMethod("scheduleLoadStop"), 12611988Sandreas.sandberg@arm.com PyBindMethod("getCurrentInstCount"), 12711988Sandreas.sandberg@arm.com ] 1289254SAndreas.Sandberg@arm.com 1299518SAndreas.Sandberg@ARM.com @classmethod 1309518SAndreas.Sandberg@ARM.com def memory_mode(cls): 1319518SAndreas.Sandberg@ARM.com """Which memory mode does this CPU require?""" 1329518SAndreas.Sandberg@ARM.com return 'invalid' 1339518SAndreas.Sandberg@ARM.com 1349518SAndreas.Sandberg@ARM.com @classmethod 1359518SAndreas.Sandberg@ARM.com def require_caches(cls): 1369518SAndreas.Sandberg@ARM.com """Does the CPU model require caches? 1379518SAndreas.Sandberg@ARM.com 1389518SAndreas.Sandberg@ARM.com Some CPU models might make assumptions that require them to 1399518SAndreas.Sandberg@ARM.com have caches. 1409518SAndreas.Sandberg@ARM.com """ 1419518SAndreas.Sandberg@ARM.com return False 1429518SAndreas.Sandberg@ARM.com 1439518SAndreas.Sandberg@ARM.com @classmethod 1449518SAndreas.Sandberg@ARM.com def support_take_over(cls): 1459518SAndreas.Sandberg@ARM.com """Does the CPU model support CPU takeOverFrom?""" 1469518SAndreas.Sandberg@ARM.com return False 1479518SAndreas.Sandberg@ARM.com 1489254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1499254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1509254SAndreas.Sandberg@arm.com 1519254SAndreas.Sandberg@arm.com 1522901SN/A system = Param.System(Parent.any, "system object") 1535712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 15410190Sakash.bagdia@arm.com socket_id = Param.Unsigned(0, "Physical Socket identifier") 1555529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 15612276Sanouk.vanlaer@arm.com pwr_gating_latency = Param.Cycles(300, 15712276Sanouk.vanlaer@arm.com "Latency to enter power gating state when all contexts are suspended") 1585529Snate@binkert.org 15912277Sjose.marinho@arm.com power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ 16012277Sjose.marinho@arm.com "to the OFF power state after all thread are disabled for "\ 16112277Sjose.marinho@arm.com "pwr_gating_latency cycles") 16212277Sjose.marinho@arm.com 1635529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1649161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1655529Snate@binkert.org 1665821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1673170SN/A 16811877Sbrandon.potter@amd.com syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") 16911877Sbrandon.potter@amd.com 1705780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1715780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1725780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1735780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1745780Ssteve.reinhardt@amd.com 1758784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1768784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1778784Sgblack@eecs.umich.edu 17812122Sjose.marinho@arm.com wait_for_remote_gdb = Param.Bool(False, 17912122Sjose.marinho@arm.com "Wait for a remote GDB connection"); 18012122Sjose.marinho@arm.com 1818793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1821310SN/A 18312434Sgabeblack@google.com dtb = Param.BaseTLB(ArchDTB(), "Data TLB") 18412434Sgabeblack@google.com itb = Param.BaseTLB(ArchITB(), "Instruction TLB") 18514147Sgabeblack@google.com if buildEnv['TARGET_ISA'] == 'arm': 18610037SARM gem5 Developers istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 18710037SARM gem5 Developers dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 1886691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1896691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 19014147Sgabeblack@google.com interrupts = ArchInterruptsParam([], "Interrupt Controller") 19114147Sgabeblack@google.com isa = ArchISAsParam([], "ISA instance") 1924997Sgblack@eecs.umich.edu 1931310SN/A max_insts_all_threads = Param.Counter(0, 1941310SN/A "terminate when all threads have reached this inst count") 1951310SN/A max_insts_any_thread = Param.Counter(0, 1961310SN/A "terminate when any thread reaches this inst count") 1979647Sdam.sunwoo@arm.com simpoint_start_insts = VectorParam.Counter([], 1989647Sdam.sunwoo@arm.com "starting instruction counts of simpoints") 1991310SN/A max_loads_all_threads = Param.Counter(0, 2001310SN/A "terminate when all threads have reached this load count") 2011310SN/A max_loads_any_thread = Param.Counter(0, 2021310SN/A "terminate when any thread reaches this load count") 2039180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 2049180Sandreas.hansson@arm.com "frequency to print out the progress message") 2051310SN/A 2069433SAndreas.Sandberg@ARM.com switched_out = Param.Bool(False, 2079433SAndreas.Sandberg@ARM.com "Leave the CPU switched out after startup (used when switching " \ 2089433SAndreas.Sandberg@ARM.com "between CPU models)") 2091634SN/A 2104776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2114776Sgblack@eecs.umich.edu 2128839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 2138839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 2148707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 2158707Sandreas.hansson@arm.com 2168756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2178707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2187876Sgblack@eecs.umich.edu 2198839Sandreas.hansson@arm.com _uncached_slave_ports = [] 2208839Sandreas.hansson@arm.com _uncached_master_ports = [] 2218745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 22211150Smitch.hayenga@arm.com _uncached_slave_ports += ["interrupts[0].pio", 22311150Smitch.hayenga@arm.com "interrupts[0].int_slave"] 22411150Smitch.hayenga@arm.com _uncached_master_ports += ["interrupts[0].int_master"] 2252998SN/A 2268863Snilay@cs.wisc.edu def createInterruptController(self): 22714147Sgabeblack@google.com self.interrupts = [ArchInterrupts() for i in range(self.numThreads)] 2288863Snilay@cs.wisc.edu 2297876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2307876Sgblack@eecs.umich.edu for p in self._cached_ports: 2318839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2327404SAli.Saidi@ARM.com 2337876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2348839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2358839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2368839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2378839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2387876Sgblack@eecs.umich.edu 2397876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2407876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2417876Sgblack@eecs.umich.edu if not uncached_bus: 2427876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2437876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2442998SN/A 2457868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2462998SN/A self.icache = ic 2472998SN/A self.dcache = dc 2482998SN/A self.icache_port = ic.cpu_side 2492998SN/A self.dcache_port = dc.cpu_side 2507876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2518796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2528796Sgblack@eecs.umich.edu if iwc and dwc: 2538796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2548796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 25510717Sandreas.hansson@arm.com self.itb.walker.port = iwc.cpu_side 25610717Sandreas.hansson@arm.com self.dtb.walker.port = dwc.cpu_side 2578796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2588796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2598796Sgblack@eecs.umich.edu else: 2608796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2618887Sgeoffrey.blake@arm.com 2628809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 2638809Sgblack@eecs.umich.edu # functional accesses only 2648887Sgeoffrey.blake@arm.com if self.checker != NULL: 2658809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 2668809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 2672998SN/A 26812440Sxiaoyuma@google.com def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, 26912440Sxiaoyuma@google.com xbar=None): 2707868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 27112440Sxiaoyuma@google.com self.toL2Bus = xbar if xbar else L2XBar() 2727876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 2732998SN/A self.l2cache = l2c 2748839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 2757876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 2768887Sgeoffrey.blake@arm.com 2779384SAndreas.Sandberg@arm.com def createThreads(self): 27812325Sandreas.sandberg@arm.com # If no ISAs have been created, assume that the user wants the 27912325Sandreas.sandberg@arm.com # default ISA. 28012325Sandreas.sandberg@arm.com if len(self.isa) == 0: 28114147Sgabeblack@google.com self.isa = [ ArchISA() for i in range(self.numThreads) ] 28212325Sandreas.sandberg@arm.com else: 28312325Sandreas.sandberg@arm.com if len(self.isa) != int(self.numThreads): 28412325Sandreas.sandberg@arm.com raise RuntimeError("Number of ISA instances doesn't " 28512325Sandreas.sandberg@arm.com "match thread count") 2869384SAndreas.Sandberg@arm.com if self.checker != NULL: 2879384SAndreas.Sandberg@arm.com self.checker.createThreads() 2889384SAndreas.Sandberg@arm.com 2898887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 2908887Sgeoffrey.blake@arm.com pass 29112470Sglenn.bergmans@arm.com 29212470Sglenn.bergmans@arm.com def createPhandleKey(self, thread): 29312470Sglenn.bergmans@arm.com # This method creates a unique key for this cpu as a function of a 29412470Sglenn.bergmans@arm.com # certain thread 29512470Sglenn.bergmans@arm.com return 'CPU-%d-%d-%d' % (self.socket_id, self.cpu_id, thread) 29612470Sglenn.bergmans@arm.com 29712470Sglenn.bergmans@arm.com #Generate simple CPU Device Tree structure 29812470Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 29912470Sglenn.bergmans@arm.com """Generate cpu nodes for each thread and the corresponding part of the 30012470Sglenn.bergmans@arm.com cpu-map node. Note that this implementation does not support clusters 30112470Sglenn.bergmans@arm.com of clusters. Note that GEM5 is not compatible with the official way of 30212470Sglenn.bergmans@arm.com numbering cores as defined in the Device Tree documentation. Where the 30312470Sglenn.bergmans@arm.com cpu_id needs to reset to 0 for each cluster by specification, GEM5 30412470Sglenn.bergmans@arm.com expects the cpu_id to be globally unique and incremental. This 30512470Sglenn.bergmans@arm.com generated node adheres the GEM5 way of doing things.""" 30612470Sglenn.bergmans@arm.com if bool(self.switched_out): 30712470Sglenn.bergmans@arm.com return 30812470Sglenn.bergmans@arm.com 30912470Sglenn.bergmans@arm.com cpus_node = FdtNode('cpus') 31012470Sglenn.bergmans@arm.com cpus_node.append(state.CPUCellsProperty()) 31112470Sglenn.bergmans@arm.com #Special size override of 0 31212470Sglenn.bergmans@arm.com cpus_node.append(FdtPropertyWords('#size-cells', [0])) 31312470Sglenn.bergmans@arm.com 31412470Sglenn.bergmans@arm.com # Generate cpu nodes 31512470Sglenn.bergmans@arm.com for i in range(int(self.numThreads)): 31612470Sglenn.bergmans@arm.com reg = (int(self.socket_id)<<8) + int(self.cpu_id) + i 31712470Sglenn.bergmans@arm.com node = FdtNode("cpu@%x" % reg) 31812470Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", "cpu")) 31912470Sglenn.bergmans@arm.com node.appendCompatible(["gem5,arm-cpu"]) 32012470Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", state.CPUAddrCells(reg))) 32112470Sglenn.bergmans@arm.com platform, found = self.system.unproxy(self).find_any(Platform) 32212470Sglenn.bergmans@arm.com if found: 32312470Sglenn.bergmans@arm.com platform.annotateCpuDeviceNode(node, state) 32412470Sglenn.bergmans@arm.com else: 32512470Sglenn.bergmans@arm.com warn("Platform not found for device tree generation; " \ 32612470Sglenn.bergmans@arm.com "system or multiple CPUs may not start") 32712470Sglenn.bergmans@arm.com 32813711Sandreas.sandberg@arm.com freq = int(self.clk_domain.unproxy(self).clock[0].frequency) 32912470Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clock-frequency", freq)) 33012470Sglenn.bergmans@arm.com 33112470Sglenn.bergmans@arm.com # Unique key for this CPU 33212470Sglenn.bergmans@arm.com phandle_key = self.createPhandleKey(i) 33312470Sglenn.bergmans@arm.com node.appendPhandle(phandle_key) 33412470Sglenn.bergmans@arm.com cpus_node.append(node) 33512470Sglenn.bergmans@arm.com 33612470Sglenn.bergmans@arm.com yield cpus_node 337