1/*
2 * Copyright (c) 2010-2012, 2015, 2017, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "cpu/simple/base.hh"
45
46#include "arch/stacktrace.hh"
47#include "arch/utility.hh"
48#include "arch/vtophys.hh"
49#include "base/cp_annotate.hh"
50#include "base/cprintf.hh"
51#include "base/inifile.hh"
52#include "base/loader/symtab.hh"
53#include "base/logging.hh"
54#include "base/pollevent.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/base.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/checker/thread_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/pred/bpred_unit.hh"
63#include "cpu/profile.hh"
64#include "cpu/simple/exec_context.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/smt.hh"
67#include "cpu/static_inst.hh"
68#include "cpu/thread_context.hh"
69#include "debug/Decode.hh"
70#include "debug/Fetch.hh"
71#include "debug/Quiesce.hh"
72#include "mem/packet.hh"
73#include "mem/request.hh"
74#include "params/BaseSimpleCPU.hh"
75#include "sim/byteswap.hh"
76#include "sim/debug.hh"
77#include "sim/faults.hh"
78#include "sim/full_system.hh"
79#include "sim/sim_events.hh"
80#include "sim/sim_object.hh"
81#include "sim/stats.hh"
82#include "sim/system.hh"
83
84using namespace std;
85using namespace TheISA;
86
87BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
88    : BaseCPU(p),
89      curThread(0),
90      branchPred(p->branchPred),
91      traceData(NULL),
92      inst(),
93      _status(Idle)
94{
95    SimpleThread *thread;
96
97    for (unsigned i = 0; i < numThreads; i++) {
98        if (FullSystem) {
99            thread = new SimpleThread(this, i, p->system,
100                                      p->itb, p->dtb, p->isa[i]);
101        } else {
102            thread = new SimpleThread(this, i, p->system, p->workload[i],
103                                      p->itb, p->dtb, p->isa[i]);
104        }
105        threadInfo.push_back(new SimpleExecContext(this, thread));
106        ThreadContext *tc = thread->getTC();
107        threadContexts.push_back(tc);
108    }
109
110    if (p->checker) {
111        if (numThreads != 1)
112            fatal("Checker currently does not support SMT");
113
114        BaseCPU *temp_checker = p->checker;
115        checker = dynamic_cast<CheckerCPU *>(temp_checker);
116        checker->setSystem(p->system);
117        // Manipulate thread context
118        ThreadContext *cpu_tc = threadContexts[0];
119        threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
120    } else {
121        checker = NULL;
122    }
123}
124
125void
126BaseSimpleCPU::init()
127{
128    BaseCPU::init();
129
130    for (auto tc : threadContexts) {
131        // Initialise the ThreadContext's memory proxies
132        tc->initMemProxies(tc);
133
134        if (FullSystem && !params()->switched_out) {
135            // initialize CPU, including PC
136            TheISA::initCPU(tc, tc->contextId());
137        }
138    }
139}
140
141void
142BaseSimpleCPU::checkPcEventQueue()
143{
144    Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
145    do {
146        oldpc = pc;
147        system->pcEventQueue.service(threadContexts[curThread]);
148        pc = threadInfo[curThread]->thread->instAddr();
149    } while (oldpc != pc);
150}
151
152void
153BaseSimpleCPU::swapActiveThread()
154{
155    if (numThreads > 1) {
156        if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
157             !threadInfo[curThread]->stayAtPC) {
158            // Swap active threads
159            if (!activeThreads.empty()) {
160                curThread = activeThreads.front();
161                activeThreads.pop_front();
162                activeThreads.push_back(curThread);
163            }
164        }
165    }
166}
167
168void
169BaseSimpleCPU::countInst()
170{
171    SimpleExecContext& t_info = *threadInfo[curThread];
172
173    if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
174        t_info.numInst++;
175        t_info.numInsts++;
176
177        system->totalNumInsts++;
178        t_info.thread->funcExeInst++;
179    }
180    t_info.numOp++;
181    t_info.numOps++;
182}
183
184Counter
185BaseSimpleCPU::totalInsts() const
186{
187    Counter total_inst = 0;
188    for (auto& t_info : threadInfo) {
189        total_inst += t_info->numInst;
190    }
191
192    return total_inst;
193}
194
195Counter
196BaseSimpleCPU::totalOps() const
197{
198    Counter total_op = 0;
199    for (auto& t_info : threadInfo) {
200        total_op += t_info->numOp;
201    }
202
203    return total_op;
204}
205
206BaseSimpleCPU::~BaseSimpleCPU()
207{
208}
209
210void
211BaseSimpleCPU::haltContext(ThreadID thread_num)
212{
213    // for now, these are equivalent
214    suspendContext(thread_num);
215    updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
216}
217
218
219void
220BaseSimpleCPU::regStats()
221{
222    using namespace Stats;
223
224    BaseCPU::regStats();
225
226    for (ThreadID tid = 0; tid < numThreads; tid++) {
227        SimpleExecContext& t_info = *threadInfo[tid];
228
229        std::string thread_str = name();
230        if (numThreads > 1)
231            thread_str += ".thread" + std::to_string(tid);
232
233        t_info.numInsts
234            .name(thread_str + ".committedInsts")
235            .desc("Number of instructions committed")
236            ;
237
238        t_info.numOps
239            .name(thread_str + ".committedOps")
240            .desc("Number of ops (including micro ops) committed")
241            ;
242
243        t_info.numIntAluAccesses
244            .name(thread_str + ".num_int_alu_accesses")
245            .desc("Number of integer alu accesses")
246            ;
247
248        t_info.numFpAluAccesses
249            .name(thread_str + ".num_fp_alu_accesses")
250            .desc("Number of float alu accesses")
251            ;
252
253        t_info.numVecAluAccesses
254            .name(thread_str + ".num_vec_alu_accesses")
255            .desc("Number of vector alu accesses")
256            ;
257
258        t_info.numCallsReturns
259            .name(thread_str + ".num_func_calls")
260            .desc("number of times a function call or return occured")
261            ;
262
263        t_info.numCondCtrlInsts
264            .name(thread_str + ".num_conditional_control_insts")
265            .desc("number of instructions that are conditional controls")
266            ;
267
268        t_info.numIntInsts
269            .name(thread_str + ".num_int_insts")
270            .desc("number of integer instructions")
271            ;
272
273        t_info.numFpInsts
274            .name(thread_str + ".num_fp_insts")
275            .desc("number of float instructions")
276            ;
277
278        t_info.numVecInsts
279            .name(thread_str + ".num_vec_insts")
280            .desc("number of vector instructions")
281            ;
282
283        t_info.numIntRegReads
284            .name(thread_str + ".num_int_register_reads")
285            .desc("number of times the integer registers were read")
286            ;
287
288        t_info.numIntRegWrites
289            .name(thread_str + ".num_int_register_writes")
290            .desc("number of times the integer registers were written")
291            ;
292
293        t_info.numFpRegReads
294            .name(thread_str + ".num_fp_register_reads")
295            .desc("number of times the floating registers were read")
296            ;
297
298        t_info.numFpRegWrites
299            .name(thread_str + ".num_fp_register_writes")
300            .desc("number of times the floating registers were written")
301            ;
302
303        t_info.numVecRegReads
304            .name(thread_str + ".num_vec_register_reads")
305            .desc("number of times the vector registers were read")
306            ;
307
308        t_info.numVecRegWrites
309            .name(thread_str + ".num_vec_register_writes")
310            .desc("number of times the vector registers were written")
311            ;
312
313        t_info.numCCRegReads
314            .name(thread_str + ".num_cc_register_reads")
315            .desc("number of times the CC registers were read")
316            .flags(nozero)
317            ;
318
319        t_info.numCCRegWrites
320            .name(thread_str + ".num_cc_register_writes")
321            .desc("number of times the CC registers were written")
322            .flags(nozero)
323            ;
324
325        t_info.numMemRefs
326            .name(thread_str + ".num_mem_refs")
327            .desc("number of memory refs")
328            ;
329
330        t_info.numStoreInsts
331            .name(thread_str + ".num_store_insts")
332            .desc("Number of store instructions")
333            ;
334
335        t_info.numLoadInsts
336            .name(thread_str + ".num_load_insts")
337            .desc("Number of load instructions")
338            ;
339
340        t_info.notIdleFraction
341            .name(thread_str + ".not_idle_fraction")
342            .desc("Percentage of non-idle cycles")
343            ;
344
345        t_info.idleFraction
346            .name(thread_str + ".idle_fraction")
347            .desc("Percentage of idle cycles")
348            ;
349
350        t_info.numBusyCycles
351            .name(thread_str + ".num_busy_cycles")
352            .desc("Number of busy cycles")
353            ;
354
355        t_info.numIdleCycles
356            .name(thread_str + ".num_idle_cycles")
357            .desc("Number of idle cycles")
358            ;
359
360        t_info.icacheStallCycles
361            .name(thread_str + ".icache_stall_cycles")
362            .desc("ICache total stall cycles")
363            .prereq(t_info.icacheStallCycles)
364            ;
365
366        t_info.dcacheStallCycles
367            .name(thread_str + ".dcache_stall_cycles")
368            .desc("DCache total stall cycles")
369            .prereq(t_info.dcacheStallCycles)
370            ;
371
372        t_info.statExecutedInstType
373            .init(Enums::Num_OpClass)
374            .name(thread_str + ".op_class")
375            .desc("Class of executed instruction")
376            .flags(total | pdf | dist)
377            ;
378
379        for (unsigned i = 0; i < Num_OpClasses; ++i) {
380            t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
381        }
382
383        t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
384        t_info.numIdleCycles = t_info.idleFraction * numCycles;
385        t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
386
387        t_info.numBranches
388            .name(thread_str + ".Branches")
389            .desc("Number of branches fetched")
390            .prereq(t_info.numBranches);
391
392        t_info.numPredictedBranches
393            .name(thread_str + ".predictedBranches")
394            .desc("Number of branches predicted as taken")
395            .prereq(t_info.numPredictedBranches);
396
397        t_info.numBranchMispred
398            .name(thread_str + ".BranchMispred")
399            .desc("Number of branch mispredictions")
400            .prereq(t_info.numBranchMispred);
401    }
402}
403
404void
405BaseSimpleCPU::resetStats()
406{
407    for (auto &thread_info : threadInfo) {
408        thread_info->notIdleFraction = (_status != Idle);
409    }
410}
411
412void
413BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
414{
415    assert(_status == Idle || _status == Running);
416
417    threadInfo[tid]->thread->serialize(cp);
418}
419
420void
421BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
422{
423    threadInfo[tid]->thread->unserialize(cp);
424}
425
426void
427change_thread_state(ThreadID tid, int activate, int priority)
428{
429}
430
431Addr
432BaseSimpleCPU::dbg_vtophys(Addr addr)
433{
434    return vtophys(threadContexts[curThread], addr);
435}
436
437void
438BaseSimpleCPU::wakeup(ThreadID tid)
439{
440    getCpuAddrMonitor(tid)->gotWakeup = true;
441
442    if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
443        DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
444        threadInfo[tid]->thread->activate();
445    }
446}
447
448void
449BaseSimpleCPU::checkForInterrupts()
450{
451    SimpleExecContext&t_info = *threadInfo[curThread];
452    SimpleThread* thread = t_info.thread;
453    ThreadContext* tc = thread->getTC();
454
455    if (checkInterrupts(tc)) {
456        Fault interrupt = interrupts[curThread]->getInterrupt(tc);
457
458        if (interrupt != NoFault) {
459            t_info.fetchOffset = 0;
460            interrupts[curThread]->updateIntrInfo(tc);
461            interrupt->invoke(tc);
462            thread->decoder.reset();
463        }
464    }
465}
466
467
468void
469BaseSimpleCPU::setupFetchRequest(const RequestPtr &req)
470{
471    SimpleExecContext &t_info = *threadInfo[curThread];
472    SimpleThread* thread = t_info.thread;
473
474    Addr instAddr = thread->instAddr();
475    Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
476
477    // set up memory request for instruction fetch
478    DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
479
480    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
481                 instMasterId(), instAddr);
482}
483
484
485void
486BaseSimpleCPU::preExecute()
487{
488    SimpleExecContext &t_info = *threadInfo[curThread];
489    SimpleThread* thread = t_info.thread;
490
491    // maintain $r0 semantics
492    thread->setIntReg(ZeroReg, 0);
493#if THE_ISA == ALPHA_ISA
494    thread->setFloatReg(ZeroReg, 0);
495#endif // ALPHA_ISA
496
497    // resets predicates
498    t_info.setPredicate(true);
499    t_info.setMemAccPredicate(true);
500
501    // check for instruction-count-based events
502    comInstEventQueue[curThread]->serviceEvents(t_info.numInst);
503    system->instEventQueue.serviceEvents(system->totalNumInsts);
504
505    // decode the instruction
506    inst = gtoh(inst);
507
508    TheISA::PCState pcState = thread->pcState();
509
510    if (isRomMicroPC(pcState.microPC())) {
511        t_info.stayAtPC = false;
512        curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
513                                                  curMacroStaticInst);
514    } else if (!curMacroStaticInst) {
515        //We're not in the middle of a macro instruction
516        StaticInstPtr instPtr = NULL;
517
518        TheISA::Decoder *decoder = &(thread->decoder);
519
520        //Predecode, ie bundle up an ExtMachInst
521        //If more fetch data is needed, pass it in.
522        Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
523        //if (decoder->needMoreBytes())
524            decoder->moreBytes(pcState, fetchPC, inst);
525        //else
526        //    decoder->process();
527
528        //Decode an instruction if one is ready. Otherwise, we'll have to
529        //fetch beyond the MachInst at the current pc.
530        instPtr = decoder->decode(pcState);
531        if (instPtr) {
532            t_info.stayAtPC = false;
533            thread->pcState(pcState);
534        } else {
535            t_info.stayAtPC = true;
536            t_info.fetchOffset += sizeof(MachInst);
537        }
538
539        //If we decoded an instruction and it's microcoded, start pulling
540        //out micro ops
541        if (instPtr && instPtr->isMacroop()) {
542            curMacroStaticInst = instPtr;
543            curStaticInst =
544                curMacroStaticInst->fetchMicroop(pcState.microPC());
545        } else {
546            curStaticInst = instPtr;
547        }
548    } else {
549        //Read the next micro op from the macro op
550        curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
551    }
552
553    //If we decoded an instruction this "tick", record information about it.
554    if (curStaticInst) {
555#if TRACING_ON
556        traceData = tracer->getInstRecord(curTick(), thread->getTC(),
557                curStaticInst, thread->pcState(), curMacroStaticInst);
558
559        DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
560                curStaticInst->getName(), curStaticInst->machInst);
561#endif // TRACING_ON
562    }
563
564    if (branchPred && curStaticInst &&
565        curStaticInst->isControl()) {
566        // Use a fake sequence number since we only have one
567        // instruction in flight at the same time.
568        const InstSeqNum cur_sn(0);
569        t_info.predPC = thread->pcState();
570        const bool predict_taken(
571            branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
572                                curThread));
573
574        if (predict_taken)
575            ++t_info.numPredictedBranches;
576    }
577}
578
579void
580BaseSimpleCPU::postExecute()
581{
582    SimpleExecContext &t_info = *threadInfo[curThread];
583    SimpleThread* thread = t_info.thread;
584
585    assert(curStaticInst);
586
587    TheISA::PCState pc = threadContexts[curThread]->pcState();
588    Addr instAddr = pc.instAddr();
589    if (FullSystem && thread->profile) {
590        bool usermode = TheISA::inUserMode(threadContexts[curThread]);
591        thread->profilePC = usermode ? 1 : instAddr;
592        ProfileNode *node = thread->profile->consume(threadContexts[curThread],
593                                                     curStaticInst);
594        if (node)
595            thread->profileNode = node;
596    }
597
598    if (curStaticInst->isMemRef()) {
599        t_info.numMemRefs++;
600    }
601
602    if (curStaticInst->isLoad()) {
603        ++t_info.numLoad;
604        comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad);
605    }
606
607    if (CPA::available()) {
608        CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
609    }
610
611    if (curStaticInst->isControl()) {
612        ++t_info.numBranches;
613    }
614
615    /* Power model statistics */
616    //integer alu accesses
617    if (curStaticInst->isInteger()){
618        t_info.numIntAluAccesses++;
619        t_info.numIntInsts++;
620    }
621
622    //float alu accesses
623    if (curStaticInst->isFloating()){
624        t_info.numFpAluAccesses++;
625        t_info.numFpInsts++;
626    }
627
628    //vector alu accesses
629    if (curStaticInst->isVector()){
630        t_info.numVecAluAccesses++;
631        t_info.numVecInsts++;
632    }
633
634    //number of function calls/returns to get window accesses
635    if (curStaticInst->isCall() || curStaticInst->isReturn()){
636        t_info.numCallsReturns++;
637    }
638
639    //the number of branch predictions that will be made
640    if (curStaticInst->isCondCtrl()){
641        t_info.numCondCtrlInsts++;
642    }
643
644    //result bus acceses
645    if (curStaticInst->isLoad()){
646        t_info.numLoadInsts++;
647    }
648
649    if (curStaticInst->isStore() || curStaticInst->isAtomic()){
650        t_info.numStoreInsts++;
651    }
652    /* End power model statistics */
653
654    t_info.statExecutedInstType[curStaticInst->opClass()]++;
655
656    if (FullSystem)
657        traceFunctions(instAddr);
658
659    if (traceData) {
660        traceData->dump();
661        delete traceData;
662        traceData = NULL;
663    }
664
665    // Call CPU instruction commit probes
666    probeInstCommit(curStaticInst, instAddr);
667}
668
669void
670BaseSimpleCPU::advancePC(const Fault &fault)
671{
672    SimpleExecContext &t_info = *threadInfo[curThread];
673    SimpleThread* thread = t_info.thread;
674
675    const bool branching(thread->pcState().branching());
676
677    //Since we're moving to a new pc, zero out the offset
678    t_info.fetchOffset = 0;
679    if (fault != NoFault) {
680        curMacroStaticInst = StaticInst::nullStaticInstPtr;
681        fault->invoke(threadContexts[curThread], curStaticInst);
682        thread->decoder.reset();
683    } else {
684        if (curStaticInst) {
685            if (curStaticInst->isLastMicroop())
686                curMacroStaticInst = StaticInst::nullStaticInstPtr;
687            TheISA::PCState pcState = thread->pcState();
688            TheISA::advancePC(pcState, curStaticInst);
689            thread->pcState(pcState);
690        }
691    }
692
693    if (branchPred && curStaticInst && curStaticInst->isControl()) {
694        // Use a fake sequence number since we only have one
695        // instruction in flight at the same time.
696        const InstSeqNum cur_sn(0);
697
698        if (t_info.predPC == thread->pcState()) {
699            // Correctly predicted branch
700            branchPred->update(cur_sn, curThread);
701        } else {
702            // Mis-predicted branch
703            branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
704            ++t_info.numBranchMispred;
705        }
706    }
707}
708
709void
710BaseSimpleCPU::startup()
711{
712    BaseCPU::startup();
713    for (auto& t_info : threadInfo)
714        t_info->thread->startup();
715}
716