11689SN/A/* 213601Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2013, 2016-2019 ARM Limited 39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 151689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 472325SN/A#ifndef __CPU_O3_CPU_HH__ 482325SN/A#define __CPU_O3_CPU_HH__ 491060SN/A 501060SN/A#include <iostream> 511060SN/A#include <list> 522292SN/A#include <queue> 532292SN/A#include <set> 541681SN/A#include <vector> 551060SN/A 5612109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/types.hh" 572980Sgblack@eecs.umich.edu#include "arch/types.hh" 581060SN/A#include "base/statistics.hh" 596658Snate@binkert.org#include "config/the_isa.hh" 601717SN/A#include "cpu/o3/comm.hh" 611717SN/A#include "cpu/o3/cpu_policy.hh" 622292SN/A#include "cpu/o3/scoreboard.hh" 632292SN/A#include "cpu/o3/thread_state.hh" 648229Snate@binkert.org#include "cpu/activity.hh" 658229Snate@binkert.org#include "cpu/base.hh" 668229Snate@binkert.org#include "cpu/simple_thread.hh" 678229Snate@binkert.org#include "cpu/timebuf.hh" 682817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 698229Snate@binkert.org#include "params/DerivO3CPU.hh" 701060SN/A#include "sim/process.hh" 711060SN/A 722316SN/Atemplate <class> 732316SN/Aclass Checker; 742680Sktlim@umich.educlass ThreadContext; 752817Sksewell@umich.edutemplate <class> 762817Sksewell@umich.educlass O3ThreadContext; 772843Sktlim@umich.edu 782843Sktlim@umich.educlass Checkpoint; 791060SN/Aclass Process; 801060SN/A 818737Skoansin.tan@gmail.comstruct BaseCPUParams; 825529Snate@binkert.org 832733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 841060SN/A{ 851060SN/A //Stuff that's pretty ISA independent will go here. 861060SN/A public: 875529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 882292SN/A 892292SN/A void regStats(); 901060SN/A}; 911060SN/A 922348SN/A/** 932348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 942348SN/A * within it, as well as all of the time buffers between stages. The 952348SN/A * tick() function for the CPU is defined here. 962348SN/A */ 971060SN/Atemplate <class Impl> 982733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 991060SN/A{ 1001060SN/A public: 1012325SN/A // Typedefs from the Impl here. 1021060SN/A typedef typename Impl::CPUPol CPUPolicy; 1031061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1044329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1051060SN/A 10612109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 10712109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10812109SRekai.GonzalezAlberquilla@arm.com 10913610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 11013610Sgiacomo.gabrielli@arm.com 1115595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1122292SN/A typedef O3ThreadState<Impl> Thread; 1132292SN/A 1142292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1152292SN/A 1162817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1172829Sksewell@umich.edu 1181060SN/A public: 1191060SN/A enum Status { 1201060SN/A Running, 1211060SN/A Idle, 1221060SN/A Halted, 1232307SN/A Blocked, 1242307SN/A SwitchedOut 1251060SN/A }; 1261060SN/A 12712406Sgabeblack@google.com BaseTLB *itb; 12812406Sgabeblack@google.com BaseTLB *dtb; 12913590Srekai.gonzalezalberquilla@arm.com using LSQRequest = typename LSQ<Impl>::LSQRequest; 1303781Sgblack@eecs.umich.edu 1312292SN/A /** Overall CPU status. */ 1321060SN/A Status _status; 1331060SN/A 1341060SN/A private: 1358707Sandreas.hansson@arm.com 1362292SN/A /** The tick event used for scheduling CPU ticks. */ 13712127Sspwilson2@wisc.edu EventFunctionWrapper tickEvent; 1381060SN/A 13913641Sqtt2@cornell.edu /** The exit event used for terminating all ready-to-exit threads */ 14013641Sqtt2@cornell.edu EventFunctionWrapper threadExitEvent; 14113641Sqtt2@cornell.edu 1422292SN/A /** Schedule tick event, regardless of its current state. */ 1439180Sandreas.hansson@arm.com void scheduleTickEvent(Cycles delay) 1441060SN/A { 1451060SN/A if (tickEvent.squashed()) 1469179Sandreas.hansson@arm.com reschedule(tickEvent, clockEdge(delay)); 1471060SN/A else if (!tickEvent.scheduled()) 1489179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 1491060SN/A } 1501060SN/A 1512292SN/A /** Unschedule tick event, regardless of its current state. */ 1521060SN/A void unscheduleTickEvent() 1531060SN/A { 1541060SN/A if (tickEvent.scheduled()) 1551060SN/A tickEvent.squash(); 1561060SN/A } 1571060SN/A 1589444SAndreas.Sandberg@ARM.com /** 15910913Sandreas.sandberg@arm.com * Check if the pipeline has drained and signal drain done. 1609444SAndreas.Sandberg@ARM.com * 1619444SAndreas.Sandberg@ARM.com * This method checks if a drain has been requested and if the CPU 1629444SAndreas.Sandberg@ARM.com * has drained successfully (i.e., there are no instructions in 1639444SAndreas.Sandberg@ARM.com * the pipeline). If the CPU has drained, it deschedules the tick 1649444SAndreas.Sandberg@ARM.com * event and signals the drain manager. 1659444SAndreas.Sandberg@ARM.com * 1669444SAndreas.Sandberg@ARM.com * @return False if a drain hasn't been requested or the CPU 1679444SAndreas.Sandberg@ARM.com * hasn't drained, true otherwise. 1689444SAndreas.Sandberg@ARM.com */ 1699444SAndreas.Sandberg@ARM.com bool tryDrain(); 1709444SAndreas.Sandberg@ARM.com 1719444SAndreas.Sandberg@ARM.com /** 1729444SAndreas.Sandberg@ARM.com * Perform sanity checks after a drain. 1739444SAndreas.Sandberg@ARM.com * 1749444SAndreas.Sandberg@ARM.com * This method is called from drain() when it has determined that 1759444SAndreas.Sandberg@ARM.com * the CPU is fully drained when gem5 is compiled with the NDEBUG 1769444SAndreas.Sandberg@ARM.com * macro undefined. The intention of this method is to do more 1779444SAndreas.Sandberg@ARM.com * extensive tests than the isDrained() method to weed out any 1789444SAndreas.Sandberg@ARM.com * draining bugs. 1799444SAndreas.Sandberg@ARM.com */ 1809444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 1819444SAndreas.Sandberg@ARM.com 1829444SAndreas.Sandberg@ARM.com /** Check if a system is in a drained state. */ 18314085Sgiacomo.travaglini@arm.com bool isCpuDrained() const; 1849444SAndreas.Sandberg@ARM.com 1851060SN/A public: 1862292SN/A /** Constructs a CPU with the given parameters. */ 1875595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 1882292SN/A /** Destructor. */ 1891755SN/A ~FullO3CPU(); 1901060SN/A 1912292SN/A /** Registers statistics. */ 19211169Sandreas.hansson@arm.com void regStats() override; 1931684SN/A 19410023Smatt.horsnell@ARM.com ProbePointArg<PacketPtr> *ppInstAccessComplete; 19510023Smatt.horsnell@ARM.com ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 19610023Smatt.horsnell@ARM.com 19710023Smatt.horsnell@ARM.com /** Register probe points. */ 19811169Sandreas.hansson@arm.com void regProbePoints() override; 19910023Smatt.horsnell@ARM.com 2005358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2015358Sgblack@eecs.umich.edu { 2025358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2035358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2045358Sgblack@eecs.umich.edu } 2055358Sgblack@eecs.umich.edu 2065358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2075358Sgblack@eecs.umich.edu { 2085358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2095358Sgblack@eecs.umich.edu } 2105358Sgblack@eecs.umich.edu 2115358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2125358Sgblack@eecs.umich.edu { 2135358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2145358Sgblack@eecs.umich.edu } 2155358Sgblack@eecs.umich.edu 2162292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2172292SN/A * activity to see if the CPU should deschedule itself. 2182292SN/A */ 2191684SN/A void tick(); 2201684SN/A 2212292SN/A /** Initialize the CPU */ 22211169Sandreas.hansson@arm.com void init() override; 2231060SN/A 22411169Sandreas.hansson@arm.com void startup() override; 2259427SAndreas.Sandberg@ARM.com 2262834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2272834Sksewell@umich.edu int numActiveThreads() 2282834Sksewell@umich.edu { return activeThreads.size(); } 2292834Sksewell@umich.edu 2302829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2316221Snate@binkert.org void activateThread(ThreadID tid); 2322875Sksewell@umich.edu 2332875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 2346221Snate@binkert.org void deactivateThread(ThreadID tid); 2352829Sksewell@umich.edu 2362292SN/A /** Setup CPU to insert a thread's context */ 2376221Snate@binkert.org void insertThread(ThreadID tid); 2381060SN/A 2392292SN/A /** Remove all of a thread's context from CPU */ 2406221Snate@binkert.org void removeThread(ThreadID tid); 2412292SN/A 2422292SN/A /** Count the Total Instructions Committed in the CPU. */ 24311169Sandreas.hansson@arm.com Counter totalInsts() const override; 2448834Satgutier@umich.edu 2458834Satgutier@umich.edu /** Count the Total Ops (including micro ops) committed in the CPU. */ 24611169Sandreas.hansson@arm.com Counter totalOps() const override; 2472292SN/A 2482292SN/A /** Add Thread to Active Threads List. */ 24911169Sandreas.hansson@arm.com void activateContext(ThreadID tid) override; 2502292SN/A 2512292SN/A /** Remove Thread from Active Threads List */ 25211169Sandreas.hansson@arm.com void suspendContext(ThreadID tid) override; 2532292SN/A 2542292SN/A /** Remove Thread from Active Threads List && 2552292SN/A * Remove Thread Context from CPU. 2562292SN/A */ 25711169Sandreas.hansson@arm.com void haltContext(ThreadID tid) override; 2582292SN/A 2592292SN/A /** Update The Order In Which We Process Threads. */ 2602292SN/A void updateThreadPriority(); 2612292SN/A 2629444SAndreas.Sandberg@ARM.com /** Is the CPU draining? */ 26310913Sandreas.sandberg@arm.com bool isDraining() const { return drainState() == DrainState::Draining; } 2649444SAndreas.Sandberg@ARM.com 26511168Sandreas.hansson@arm.com void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 26611168Sandreas.hansson@arm.com void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 2672864Sktlim@umich.edu 26813641Sqtt2@cornell.edu /** Insert tid to the list of threads trying to exit */ 26913641Sqtt2@cornell.edu void addThreadToExitingList(ThreadID tid); 27013641Sqtt2@cornell.edu 27113641Sqtt2@cornell.edu /** Is the thread trying to exit? */ 27213641Sqtt2@cornell.edu bool isThreadExiting(ThreadID tid) const; 27313641Sqtt2@cornell.edu 27413641Sqtt2@cornell.edu /** 27513641Sqtt2@cornell.edu * If a thread is trying to exit and its corresponding trap event 27613641Sqtt2@cornell.edu * has been completed, schedule an event to terminate the thread. 27713641Sqtt2@cornell.edu */ 27813641Sqtt2@cornell.edu void scheduleThreadExitEvent(ThreadID tid); 27913641Sqtt2@cornell.edu 28013641Sqtt2@cornell.edu /** Terminate all threads that are ready to exit */ 28113641Sqtt2@cornell.edu void exitThreads(); 28213641Sqtt2@cornell.edu 2832864Sktlim@umich.edu public: 2845595Sgblack@eecs.umich.edu /** Executes a syscall. 2855595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 2862292SN/A */ 28711877Sbrandon.potter@amd.com void syscall(int64_t callnum, ThreadID tid, Fault *fault); 2882292SN/A 2892843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 2902843Sktlim@umich.edu * order to stop all memory accesses. */ 29111168Sandreas.hansson@arm.com DrainState drain() override; 2922843Sktlim@umich.edu 2932843Sktlim@umich.edu /** Resumes execution after a drain. */ 29411168Sandreas.hansson@arm.com void drainResume() override; 2952292SN/A 2969444SAndreas.Sandberg@ARM.com /** 2979444SAndreas.Sandberg@ARM.com * Commit has reached a safe point to drain a thread. 2989444SAndreas.Sandberg@ARM.com * 2999444SAndreas.Sandberg@ARM.com * Commit calls this method to inform the pipeline that it has 3009444SAndreas.Sandberg@ARM.com * reached a point where it is not executed microcode and is about 3019444SAndreas.Sandberg@ARM.com * to squash uncommitted instructions to fully drain the pipeline. 3029444SAndreas.Sandberg@ARM.com */ 3039444SAndreas.Sandberg@ARM.com void commitDrained(ThreadID tid); 3042843Sktlim@umich.edu 3052843Sktlim@umich.edu /** Switches out this CPU. */ 30611169Sandreas.hansson@arm.com void switchOut() override; 3072316SN/A 3082348SN/A /** Takes over from another CPU. */ 30911169Sandreas.hansson@arm.com void takeOverFrom(BaseCPU *oldCPU) override; 3101060SN/A 31111169Sandreas.hansson@arm.com void verifyMemoryMode() const override; 3129523SAndreas.Sandberg@ARM.com 3131060SN/A /** Get the current instruction sequence number, and increment it. */ 3142316SN/A InstSeqNum getAndIncrementInstSeq() 3152316SN/A { return globalSeqNum++; } 3161060SN/A 3175595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 31810417Sandreas.hansson@arm.com void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 3195595Sgblack@eecs.umich.edu 32013601Sgiacomo.travaglini@arm.com /** Check if a change in renaming is needed for vector registers. 32113601Sgiacomo.travaglini@arm.com * The vecMode variable is updated and propagated to rename maps. 32213601Sgiacomo.travaglini@arm.com * 32313601Sgiacomo.travaglini@arm.com * @param tid ThreadID 32413601Sgiacomo.travaglini@arm.com * @param freelist list of free registers 32513601Sgiacomo.travaglini@arm.com */ 32613601Sgiacomo.travaglini@arm.com void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist); 32713601Sgiacomo.travaglini@arm.com 3285595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 3295595Sgblack@eecs.umich.edu Fault getInterrupts(); 3305595Sgblack@eecs.umich.edu 3315595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 33210379Sandreas.hansson@arm.com void processInterrupts(const Fault &interrupt); 3335595Sgblack@eecs.umich.edu 3345595Sgblack@eecs.umich.edu /** Halts the CPU. */ 3355595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3365595Sgblack@eecs.umich.edu 3372348SN/A /** Register accessors. Index refers to the physical register index. */ 3385595Sgblack@eecs.umich.edu 3395595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 34013557Sgabeblack@google.com RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 3415595Sgblack@eecs.umich.edu 3425595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 3435595Sgblack@eecs.umich.edu * might have as defined by the architecture. 3445595Sgblack@eecs.umich.edu */ 34513557Sgabeblack@google.com RegVal readMiscReg(int misc_reg, ThreadID tid); 3465595Sgblack@eecs.umich.edu 3475595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 34813582Sgabeblack@google.com void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid); 3495595Sgblack@eecs.umich.edu 3505595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 3515595Sgblack@eecs.umich.edu * might have as defined by the architecture. 3525595Sgblack@eecs.umich.edu */ 35313582Sgabeblack@google.com void setMiscReg(int misc_reg, RegVal val, ThreadID tid); 3545595Sgblack@eecs.umich.edu 35513557Sgabeblack@google.com RegVal readIntReg(PhysRegIdPtr phys_reg); 3561060SN/A 35713611Sgabeblack@google.com RegVal readFloatReg(PhysRegIdPtr phys_reg); 3582455SN/A 35912109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 36012109SRekai.GonzalezAlberquilla@arm.com 36112109SRekai.GonzalezAlberquilla@arm.com /** 36212109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register for modification. 36312109SRekai.GonzalezAlberquilla@arm.com */ 36412109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 36512109SRekai.GonzalezAlberquilla@arm.com 36613601Sgiacomo.travaglini@arm.com /** Returns current vector renaming mode */ 36713601Sgiacomo.travaglini@arm.com Enums::VecRegRenameMode vecRenameMode() const { return vecMode; } 36813601Sgiacomo.travaglini@arm.com 36913601Sgiacomo.travaglini@arm.com /** Sets the current vector renaming mode */ 37013601Sgiacomo.travaglini@arm.com void vecRenameMode(Enums::VecRegRenameMode vec_mode) 37113601Sgiacomo.travaglini@arm.com { vecMode = vec_mode; } 37213601Sgiacomo.travaglini@arm.com 37312109SRekai.GonzalezAlberquilla@arm.com /** 37412109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register lane 37512109SRekai.GonzalezAlberquilla@arm.com */ 37612109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem, int LaneIdx> 37712109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 37812109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 37912109SRekai.GonzalezAlberquilla@arm.com { 38012109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 38112109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 38212109SRekai.GonzalezAlberquilla@arm.com } 38312109SRekai.GonzalezAlberquilla@arm.com 38412109SRekai.GonzalezAlberquilla@arm.com /** 38512109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register lane 38612109SRekai.GonzalezAlberquilla@arm.com */ 38712109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem> 38812109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 38912109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 39012109SRekai.GonzalezAlberquilla@arm.com { 39112109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 39212109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecLane<VecElem>(phys_reg); 39312109SRekai.GonzalezAlberquilla@arm.com } 39412109SRekai.GonzalezAlberquilla@arm.com 39512109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 39612109SRekai.GonzalezAlberquilla@arm.com template<typename LD> 39712109SRekai.GonzalezAlberquilla@arm.com void 39812109SRekai.GonzalezAlberquilla@arm.com setVecLane(PhysRegIdPtr phys_reg, const LD& val) 39912109SRekai.GonzalezAlberquilla@arm.com { 40012109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 40112109SRekai.GonzalezAlberquilla@arm.com return regFile.setVecLane(phys_reg, val); 40212109SRekai.GonzalezAlberquilla@arm.com } 40312109SRekai.GonzalezAlberquilla@arm.com 40412109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 40512109SRekai.GonzalezAlberquilla@arm.com 40613610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const; 40713610Sgiacomo.gabrielli@arm.com 40813610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); 40913610Sgiacomo.gabrielli@arm.com 41013622Sgabeblack@google.com RegVal readCCReg(PhysRegIdPtr phys_reg); 4119920Syasuko.eckert@amd.com 41213557Sgabeblack@google.com void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 4131060SN/A 41413611Sgabeblack@google.com void setFloatReg(PhysRegIdPtr phys_reg, RegVal val); 4152455SN/A 41612109SRekai.GonzalezAlberquilla@arm.com void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 41712109SRekai.GonzalezAlberquilla@arm.com 41812109SRekai.GonzalezAlberquilla@arm.com void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 41912109SRekai.GonzalezAlberquilla@arm.com 42013610Sgiacomo.gabrielli@arm.com void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); 42113610Sgiacomo.gabrielli@arm.com 42213622Sgabeblack@google.com void setCCReg(PhysRegIdPtr phys_reg, RegVal val); 4239920Syasuko.eckert@amd.com 42413557Sgabeblack@google.com RegVal readArchIntReg(int reg_idx, ThreadID tid); 4251060SN/A 42613611Sgabeblack@google.com RegVal readArchFloatReg(int reg_idx, ThreadID tid); 4272292SN/A 42812109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 42912109SRekai.GonzalezAlberquilla@arm.com /** Read architectural vector register for modification. */ 43012109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 43112109SRekai.GonzalezAlberquilla@arm.com 43212109SRekai.GonzalezAlberquilla@arm.com /** Read architectural vector register lane. */ 43312109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem> 43412109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 43512109SRekai.GonzalezAlberquilla@arm.com readArchVecLane(int reg_idx, int lId, ThreadID tid) const 43612109SRekai.GonzalezAlberquilla@arm.com { 43712109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 43812109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 43912109SRekai.GonzalezAlberquilla@arm.com return readVecLane<VecElem>(phys_reg); 44012109SRekai.GonzalezAlberquilla@arm.com } 44112109SRekai.GonzalezAlberquilla@arm.com 44212109SRekai.GonzalezAlberquilla@arm.com 44312109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 44412109SRekai.GonzalezAlberquilla@arm.com template<typename LD> 44512109SRekai.GonzalezAlberquilla@arm.com void 44612109SRekai.GonzalezAlberquilla@arm.com setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 44712109SRekai.GonzalezAlberquilla@arm.com { 44812109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 44912109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 45012109SRekai.GonzalezAlberquilla@arm.com setVecLane(phys_reg, val); 45112109SRekai.GonzalezAlberquilla@arm.com } 45212109SRekai.GonzalezAlberquilla@arm.com 45312109SRekai.GonzalezAlberquilla@arm.com const VecElem& readArchVecElem(const RegIndex& reg_idx, 45412109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& ldx, ThreadID tid) const; 45512109SRekai.GonzalezAlberquilla@arm.com 45613610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readArchVecPredReg(int reg_idx, 45713610Sgiacomo.gabrielli@arm.com ThreadID tid) const; 45813610Sgiacomo.gabrielli@arm.com 45913610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid); 46013610Sgiacomo.gabrielli@arm.com 46113622Sgabeblack@google.com RegVal readArchCCReg(int reg_idx, ThreadID tid); 4629920Syasuko.eckert@amd.com 4632348SN/A /** Architectural register accessors. Looks up in the commit 4642348SN/A * rename table to obtain the true physical index of the 4652348SN/A * architected register first, then accesses that physical 4662348SN/A * register. 4672348SN/A */ 46813557Sgabeblack@google.com void setArchIntReg(int reg_idx, RegVal val, ThreadID tid); 4692292SN/A 47013611Sgabeblack@google.com void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid); 4712292SN/A 47213610Sgiacomo.gabrielli@arm.com void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 47313610Sgiacomo.gabrielli@arm.com ThreadID tid); 47413610Sgiacomo.gabrielli@arm.com 47512109SRekai.GonzalezAlberquilla@arm.com void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 47612109SRekai.GonzalezAlberquilla@arm.com 47712109SRekai.GonzalezAlberquilla@arm.com void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 47812109SRekai.GonzalezAlberquilla@arm.com const VecElem& val, ThreadID tid); 47912109SRekai.GonzalezAlberquilla@arm.com 48013622Sgabeblack@google.com void setArchCCReg(int reg_idx, RegVal val, ThreadID tid); 4819920Syasuko.eckert@amd.com 4827720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 4837720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 4847720Sgblack@eecs.umich.edu 4857720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 4867720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 4877720Sgblack@eecs.umich.edu 4882348SN/A /** Reads the commit PC of a specific thread. */ 4897720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 4902292SN/A 4914636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4927720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 4934636Sgblack@eecs.umich.edu 4942348SN/A /** Reads the next PC of a specific thread. */ 4957720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 4962756Sksewell@umich.edu 4975595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 4985595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 4995595Sgblack@eecs.umich.edu * state through the TC. 5005595Sgblack@eecs.umich.edu */ 5016221Snate@binkert.org void squashFromTC(ThreadID tid); 5025595Sgblack@eecs.umich.edu 5031060SN/A /** Function to add instruction onto the head of the list of the 5041060SN/A * instructions. Used when new instructions are fetched. 5051060SN/A */ 50613429Srekai.gonzalezalberquilla@arm.com ListIt addInst(const DynInstPtr &inst); 5071060SN/A 5081060SN/A /** Function to tell the CPU that an instruction has completed. */ 50913429Srekai.gonzalezalberquilla@arm.com void instDone(ThreadID tid, const DynInstPtr &inst); 5101060SN/A 5112325SN/A /** Remove an instruction from the front end of the list. There's 5122325SN/A * no restriction on location of the instruction. 5131060SN/A */ 51413429Srekai.gonzalezalberquilla@arm.com void removeFrontInst(const DynInstPtr &inst); 5151060SN/A 5162935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5172935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5186221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 5191060SN/A 5201062SN/A /** Remove all instructions younger than the given sequence number. */ 5216221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 5222292SN/A 5232348SN/A /** Removes the instruction pointed to by the iterator. */ 5246221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 5252292SN/A 5262348SN/A /** Cleans up all instructions on the remove list. */ 5272292SN/A void cleanUpRemovedInsts(); 5281062SN/A 5292348SN/A /** Debug function to print all instructions on the list. */ 5301060SN/A void dumpInsts(); 5311060SN/A 5321060SN/A public: 5335737Scws3k@cs.virginia.edu#ifndef NDEBUG 5345737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5355737Scws3k@cs.virginia.edu int instcount; 5365737Scws3k@cs.virginia.edu#endif 5375737Scws3k@cs.virginia.edu 5381060SN/A /** List of all the instructions in flight. */ 5392292SN/A std::list<DynInstPtr> instList; 5401060SN/A 5412292SN/A /** List of all the instructions that will be removed at the end of this 5422292SN/A * cycle. 5432292SN/A */ 5442292SN/A std::queue<ListIt> removeList; 5452292SN/A 5462325SN/A#ifdef DEBUG 5472348SN/A /** Debug structure to keep track of the sequence numbers still in 5482348SN/A * flight. 5492348SN/A */ 5502292SN/A std::set<InstSeqNum> snList; 5512325SN/A#endif 5522292SN/A 5532325SN/A /** Records if instructions need to be removed this cycle due to 5542325SN/A * being retired or squashed. 5552292SN/A */ 5562292SN/A bool removeInstsThisCycle; 5572292SN/A 5581060SN/A protected: 5591060SN/A /** The fetch stage. */ 5601060SN/A typename CPUPolicy::Fetch fetch; 5611060SN/A 5621060SN/A /** The decode stage. */ 5631060SN/A typename CPUPolicy::Decode decode; 5641060SN/A 5651060SN/A /** The dispatch stage. */ 5661060SN/A typename CPUPolicy::Rename rename; 5671060SN/A 5681060SN/A /** The issue/execute/writeback stages. */ 5691060SN/A typename CPUPolicy::IEW iew; 5701060SN/A 5711060SN/A /** The commit stage. */ 5721060SN/A typename CPUPolicy::Commit commit; 5731060SN/A 57412109SRekai.GonzalezAlberquilla@arm.com /** The rename mode of the vector registers */ 57512109SRekai.GonzalezAlberquilla@arm.com Enums::VecRegRenameMode vecMode; 57612109SRekai.GonzalezAlberquilla@arm.com 5771060SN/A /** The register file. */ 5789919Ssteve.reinhardt@amd.com PhysRegFile regFile; 5791060SN/A 5801060SN/A /** The free list. */ 5811060SN/A typename CPUPolicy::FreeList freeList; 5821060SN/A 5831060SN/A /** The rename map. */ 5842292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5852292SN/A 5862292SN/A /** The commit rename map. */ 5872292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5881060SN/A 5891060SN/A /** The re-order buffer. */ 5901060SN/A typename CPUPolicy::ROB rob; 5911060SN/A 5922292SN/A /** Active Threads List */ 5936221Snate@binkert.org std::list<ThreadID> activeThreads; 5942292SN/A 59513641Sqtt2@cornell.edu /** 59613641Sqtt2@cornell.edu * This is a list of threads that are trying to exit. Each thread id 59713641Sqtt2@cornell.edu * is mapped to a boolean value denoting whether the thread is ready 59813641Sqtt2@cornell.edu * to exit. 59913641Sqtt2@cornell.edu */ 60013641Sqtt2@cornell.edu std::unordered_map<ThreadID, bool> exitingThreads; 60113641Sqtt2@cornell.edu 6022292SN/A /** Integer Register Scoreboard */ 6032292SN/A Scoreboard scoreboard; 6042292SN/A 6059384SAndreas.Sandberg@arm.com std::vector<TheISA::ISA *> isa; 6066313Sgblack@eecs.umich.edu 6071060SN/A public: 6082292SN/A /** Enum to give each stage a specific index, so when calling 6092292SN/A * activateStage() or deactivateStage(), they can specify which stage 6102292SN/A * is being activated/deactivated. 6112292SN/A */ 6122292SN/A enum StageIdx { 6132292SN/A FetchIdx, 6142292SN/A DecodeIdx, 6152292SN/A RenameIdx, 6162292SN/A IEWIdx, 6172292SN/A CommitIdx, 6182292SN/A NumStages }; 6192292SN/A 6201060SN/A /** Typedefs from the Impl to get the structs that each of the 6211060SN/A * time buffers should use. 6221060SN/A */ 6231061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6241060SN/A 6251061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6261060SN/A 6271061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6281060SN/A 6291061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6301060SN/A 6311061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6321060SN/A 6331060SN/A /** The main time buffer to do backwards communication. */ 6341060SN/A TimeBuffer<TimeStruct> timeBuffer; 6351060SN/A 6361060SN/A /** The fetch stage's instruction queue. */ 6371060SN/A TimeBuffer<FetchStruct> fetchQueue; 6381060SN/A 6391060SN/A /** The decode stage's instruction queue. */ 6401060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6411060SN/A 6421060SN/A /** The rename stage's instruction queue. */ 6431060SN/A TimeBuffer<RenameStruct> renameQueue; 6441060SN/A 6451060SN/A /** The IEW stage's instruction queue. */ 6461060SN/A TimeBuffer<IEWStruct> iewQueue; 6471060SN/A 6482348SN/A private: 6492348SN/A /** The activity recorder; used to tell if the CPU has any 6502348SN/A * activity remaining or if it can go to idle and deschedule 6512348SN/A * itself. 6522348SN/A */ 6532325SN/A ActivityRecorder activityRec; 6541060SN/A 6552348SN/A public: 6562348SN/A /** Records that there was time buffer activity this cycle. */ 6572325SN/A void activityThisCycle() { activityRec.activity(); } 6582292SN/A 6592348SN/A /** Changes a stage's status to active within the activity recorder. */ 6602325SN/A void activateStage(const StageIdx idx) 6612325SN/A { activityRec.activateStage(idx); } 6622292SN/A 6632348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6642325SN/A void deactivateStage(const StageIdx idx) 6652325SN/A { activityRec.deactivateStage(idx); } 6662292SN/A 6672292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6682292SN/A void wakeCPU(); 6692260SN/A 67011168Sandreas.hansson@arm.com virtual void wakeup(ThreadID tid) override; 6715807Snate@binkert.org 6722292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6736221Snate@binkert.org ThreadID getFreeTid(); 6742292SN/A 6752292SN/A public: 6762680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6776221Snate@binkert.org ThreadContext * 6786221Snate@binkert.org tcBase(ThreadID tid) 6791681SN/A { 6802680Sktlim@umich.edu return thread[tid]->getTC(); 6812190SN/A } 6822190SN/A 6832292SN/A /** The global sequence number counter. */ 6843093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6851060SN/A 6862348SN/A /** Pointer to the checker, which can dynamically verify 6872348SN/A * instruction results at run time. This can be set to NULL if it 6882348SN/A * is not being used. 6892348SN/A */ 6908733Sgeoffrey.blake@arm.com Checker<Impl> *checker; 6912316SN/A 6922292SN/A /** Pointer to the system. */ 6931060SN/A System *system; 6941060SN/A 6952348SN/A /** Pointers to all of the threads in the CPU. */ 6962292SN/A std::vector<Thread *> thread; 6972260SN/A 6982292SN/A /** Threads Scheduled to Enter CPU */ 6992292SN/A std::list<int> cpuWaitList; 7002292SN/A 7012292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7029180Sandreas.hansson@arm.com Cycles lastRunningCycle; 7032292SN/A 7042829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7052829Sksewell@umich.edu Tick lastActivatedCycle; 7062829Sksewell@umich.edu 7072292SN/A /** Mapping for system thread id to cpu id */ 7086221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 7092292SN/A 7102292SN/A /** Available thread ids in the cpu*/ 7116221Snate@binkert.org std::vector<ThreadID> tids; 7122292SN/A 71313590Srekai.gonzalezalberquilla@arm.com /** CPU pushRequest function, forwards request to LSQ. */ 71413590Srekai.gonzalezalberquilla@arm.com Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, 71513590Srekai.gonzalezalberquilla@arm.com unsigned int size, Addr addr, Request::Flags flags, 71614297Sjordi.vaquero@metempsy.com uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr, 71713954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable = 71813954Sgiacomo.gabrielli@arm.com std::vector<bool>()) 71913954Sgiacomo.gabrielli@arm.com 72013590Srekai.gonzalezalberquilla@arm.com { 72113590Srekai.gonzalezalberquilla@arm.com return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr, 72214297Sjordi.vaquero@metempsy.com flags, res, std::move(amo_op), byteEnable); 72313590Srekai.gonzalezalberquilla@arm.com } 72413590Srekai.gonzalezalberquilla@arm.com 7255595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 72613590Srekai.gonzalezalberquilla@arm.com Fault read(LSQRequest* req, int load_idx) 7275595Sgblack@eecs.umich.edu { 72813590Srekai.gonzalezalberquilla@arm.com return this->iew.ldstQueue.read(req, load_idx); 7295595Sgblack@eecs.umich.edu } 7305595Sgblack@eecs.umich.edu 7315595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 73213590Srekai.gonzalezalberquilla@arm.com Fault write(LSQRequest* req, uint8_t *data, int store_idx) 7335595Sgblack@eecs.umich.edu { 73413590Srekai.gonzalezalberquilla@arm.com return this->iew.ldstQueue.write(req, data, store_idx); 7355595Sgblack@eecs.umich.edu } 7365595Sgblack@eecs.umich.edu 7378707Sandreas.hansson@arm.com /** Used by the fetch unit to get a hold of the instruction port. */ 73814198Sgabeblack@google.com Port & 73914195Sgabeblack@google.com getInstPort() override 74014195Sgabeblack@google.com { 74114195Sgabeblack@google.com return this->fetch.getInstPort(); 74214195Sgabeblack@google.com } 7438707Sandreas.hansson@arm.com 7446974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 74514198Sgabeblack@google.com Port & 74614194Sgabeblack@google.com getDataPort() override 74714194Sgabeblack@google.com { 74814194Sgabeblack@google.com return this->iew.ldstQueue.getDataPort(); 74914194Sgabeblack@google.com } 7506974Stjones1@inf.ed.ac.uk 7512292SN/A /** Stat for total number of times the CPU is descheduled. */ 7525999Snate@binkert.org Stats::Scalar timesIdled; 7532292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7545999Snate@binkert.org Stats::Scalar idleCycles; 7558627SAli.Saidi@ARM.com /** Stat for total number of cycles the CPU spends descheduled due to a 7568627SAli.Saidi@ARM.com * quiesce operation or waiting for an interrupt. */ 7578627SAli.Saidi@ARM.com Stats::Scalar quiesceCycles; 7582292SN/A /** Stat for the number of committed instructions per thread. */ 7595999Snate@binkert.org Stats::Vector committedInsts; 7608834Satgutier@umich.edu /** Stat for the number of committed ops (including micro ops) per thread. */ 7618834Satgutier@umich.edu Stats::Vector committedOps; 7622292SN/A /** Stat for the CPI per thread. */ 7632292SN/A Stats::Formula cpi; 7642292SN/A /** Stat for the total CPI. */ 7652292SN/A Stats::Formula totalCpi; 7662292SN/A /** Stat for the IPC per thread. */ 7672292SN/A Stats::Formula ipc; 7682292SN/A /** Stat for the total IPC. */ 7692292SN/A Stats::Formula totalIpc; 7707897Shestness@cs.utexas.edu 7717897Shestness@cs.utexas.edu //number of integer register file accesses 7727897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 7737897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 7747897Shestness@cs.utexas.edu //number of float register file accesses 7757897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 7767897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 77712109SRekai.GonzalezAlberquilla@arm.com //number of vector register file accesses 77812109SRekai.GonzalezAlberquilla@arm.com mutable Stats::Scalar vecRegfileReads; 77912109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar vecRegfileWrites; 78013610Sgiacomo.gabrielli@arm.com //number of predicate register file accesses 78113610Sgiacomo.gabrielli@arm.com mutable Stats::Scalar vecPredRegfileReads; 78213610Sgiacomo.gabrielli@arm.com Stats::Scalar vecPredRegfileWrites; 7839920Syasuko.eckert@amd.com //number of CC register file accesses 7849920Syasuko.eckert@amd.com Stats::Scalar ccRegfileReads; 7859920Syasuko.eckert@amd.com Stats::Scalar ccRegfileWrites; 7867897Shestness@cs.utexas.edu //number of misc 7877897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 7887897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 7891060SN/A}; 7901060SN/A 7912325SN/A#endif // __CPU_O3_CPU_HH__ 792