Searched refs:vaddr (Results 26 - 50 of 72) sorted by relevance

123

/gem5/src/arch/x86/
H A Dpagetable_walker.cc291 VAddr vaddr = entry.vaddr; local
302 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * dataSize;
318 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * dataSize;
346 ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * dataSize;
356 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
377 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
384 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr
550 setupWalk(Addr vaddr) argument
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H A Dpagetable.hh72 Addr vaddr; member in struct:X86ISA::TlbEntry
104 vaddr = new_vaddr;
172 read(PortProxy &p, Addr table, Addr vaddr) argument
175 entryAddr += bits(vaddr, first, last) * sizeof(PageTableEntry);
/gem5/src/sim/
H A Dprocess.cc179 Addr paddr, vaddr = map.first; local
180 bool alloc_page = !(np->pTable->translate(vaddr, paddr));
181 np->replicatePage(vaddr, paddr, otc, ntc, alloc_page);
296 Process::allocateMem(Addr vaddr, int64_t size, bool clobber) argument
300 pTable->map(vaddr, paddr, size,
306 Process::replicatePage(Addr vaddr, Addr new_paddr, ThreadContext *old_tc, argument
314 old_tc->getVirtProxy().readBlob(vaddr, buf_p, PageBytes);
319 pTable->map(vaddr, new_paddr, PageBytes, clobber);
320 new_tc->getVirtProxy().writeBlob(vaddr, buf_p, PageBytes);
325 Process::fixupStackFault(Addr vaddr) argument
384 map(Addr vaddr, Addr paddr, int size, bool cacheable) argument
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H A Dprocess.hh114 void allocateMem(Addr vaddr, int64_t size, bool clobber = false);
116 /// Attempt to fix up a fault at vaddr by allocating a page on the stack.
118 bool fixupStackFault(Addr vaddr);
150 * @param vaddr The starting virtual address of the range.
157 bool map(Addr vaddr, Addr paddr, int size, bool cacheable = true);
159 void replicatePage(Addr vaddr, Addr new_paddr, ThreadContext *old_tc,
H A Dpseudo_inst.hh72 uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
74 uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
H A DProcess.py39 def map(self, vaddr, paddr, size, cacheable=False):
69 code('bool map(Addr vaddr, Addr paddr, int sz, bool cacheable=true);')
/gem5/src/arch/mips/
H A Dfaults.hh193 Addr vaddr; member in class:MipsISA::AddressFault
196 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
205 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
240 tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
276 TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) : argument
277 TlbFault<TlbRefillFault>(asid, vaddr, vpn, store)
291 TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) : argument
292 TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store)
299 TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) : argument
300 TlbFault<TlbModifiedFault>(asid, vaddr, vp
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H A Dtlb.hh96 void insert(Addr vaddr, MipsISA::PTE &pte);
99 void demapPage(Addr vaddr, uint64_t asn) override
105 static bool validVirtualAddress(Addr vaddr);
H A Dpagetable.hh86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, argument
/gem5/src/arch/riscv/
H A Dtlb.hh95 void insert(Addr vaddr, RiscvISA::PTE &pte);
98 void demapPage(Addr vaddr, uint64_t asn) override
104 static bool validVirtualAddress(Addr vaddr);
H A Dpagetable.hh86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, argument
/gem5/src/arch/alpha/
H A Dpagetable.hh110 VAddr vaddr(_vaddr);
112 tag = vaddr.vpn();
135 VAddr vaddr(new_vaddr);
136 tag = vaddr.vpn();
H A Dtlb.cc251 VAddr vaddr = addr; local
272 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn);
275 table[nlu].tag = vaddr.vpn();
278 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
321 VAddr vaddr = addr; local
323 PageTable::iterator i = lookupTable.find(vaddr.vpn());
327 while (i != lookupTable.end() && i->first == vaddr.vpn()) {
332 if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) {
333 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
/gem5/src/arch/power/
H A Dtlb.hh65 TlbEntry(Addr asn, Addr vaddr, Addr paddr, argument
150 void insert(Addr vaddr, PowerISA::PTE &pte);
155 demapPage(Addr vaddr, uint64_t asn) override
161 static bool validVirtualAddress(Addr vaddr);
/gem5/src/arch/arm/
H A Dstage2_mmu.hh93 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId) argument
96 req->setVirt(0, vaddr, size, flags, masterId, 0);
H A Dtlb.cc570 Addr vaddr = 0; local
572 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
574 vaddr = vaddr_tainted;
583 if (vaddr & mask(flags & AlignmentMask)) {
597 if (!p->pTable->translate(vaddr, paddr))
613 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify local
630 vaddr, te->domain, is_write,
639 if (vaddr & mask(flags & AlignmentMask)) {
642 vaddr, TlbEntry::DomainType::NoAccess, is_write,
655 vaddr, ArmFaul
798 Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); local
1046 Addr vaddr = 0; local
1465 Addr vaddr = 0; local
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/gem5/src/arch/generic/
H A Dtlb.hh90 virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
152 void demapPage(Addr vaddr, uint64_t asn) override;
H A Dtlb.cc70 GenericTLB::demapPage(Addr vaddr, uint64_t asn) argument
/gem5/src/arch/sparc/
H A Dfaults.hh210 Addr vaddr; member in class:SparcISA::FastInstructionAccessMMUMiss
212 FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
214 FastInstructionAccessMMUMiss() : vaddr(0)
223 Addr vaddr; member in class:SparcISA::FastDataAccessMMUMiss
225 FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
227 FastDataAccessMMUMiss() : vaddr(0)
H A Dpagetable.hh175 translate(Addr vaddr) const
179 return (paddr() & ~mask) | (vaddr & mask);
233 TlbEntry(Addr asn, Addr vaddr, Addr paddr, argument
254 range.va = vaddr;
H A Dvtophys.cc48 vtophys(Addr vaddr) argument
/gem5/src/arch/hsail/insts/
H A Dmem.hh457 Addr vaddr = gpuDynInst->addr[i] + k * sizeof(c0); variable
462 read<c0>(vaddr);
465 vaddr, sizeof(c0), 0,
1062 Addr vaddr = gpuDynInst->addr[i] + k * sizeof(c0); variable
1066 gpuDynInst->wavefront()->ldsChunk->write<c0>(vaddr,
1070 0, vaddr, sizeof(c0), 0,
1578 Addr vaddr = gpuDynInst->addr[i]; variable
1582 *d = wavefront->ldsChunk->read<c0>(vaddr);
1585 wavefront->ldsChunk->write<c0>(vaddr,
1586 wavefront->ldsChunk->read<c0>(vaddr)
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/gem5/src/cpu/o3/
H A Dcpu.hh200 void demapPage(Addr vaddr, uint64_t asn) argument
202 this->itb->demapPage(vaddr, asn);
203 this->dtb->demapPage(vaddr, asn);
206 void demapInstPage(Addr vaddr, uint64_t asn) argument
208 this->itb->demapPage(vaddr, asn);
211 void demapDataPage(Addr vaddr, uint64_t asn) argument
213 this->dtb->demapPage(vaddr, asn);
/gem5/src/cpu/minor/
H A Dexec_context.hh409 demapPage(Addr vaddr, uint64_t asn) override
411 thread.getITBPtr()->demapPage(vaddr, asn);
412 thread.getDTBPtr()->demapPage(vaddr, asn);
432 demapInstPage(Addr vaddr, uint64_t asn) argument
434 thread.getITBPtr()->demapPage(vaddr, asn);
438 demapDataPage(Addr vaddr, uint64_t asn) argument
440 thread.getDTBPtr()->demapPage(vaddr, asn);
/gem5/src/base/
H A Dremote_gdb.cc615 BaseRemoteGDB::read(Addr vaddr, size_t size, char *data) argument
620 if (vaddr < 10) {
622 vaddr = lastaddr + lastsize;
625 DPRINTF(GDBRead, "read: addr=%#x, size=%d", vaddr, size);
628 proxy.readBlob(vaddr, data, size);
646 BaseRemoteGDB::write(Addr vaddr, size_t size, const char *data) argument
651 if (vaddr < 10) {
653 vaddr = lastaddr + lastsize;
657 DPRINTFN("write: addr=%#x, size=%d", vaddr, size);
666 proxy.writeBlob(vaddr, dat
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