1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 */
42
43#ifndef __SIM_PSEUDO_INST_HH__
44#define __SIM_PSEUDO_INST_HH__
45
46class ThreadContext;
47
48//We need the "Tick" and "Addr" data types from here
49#include "base/types.hh"
50
51namespace PseudoInst {
52
53/**
54 * Execute a decoded M5 pseudo instruction
55 *
56 * The ISA-specific code is responsible to decode the pseudo inst
57 * function number and subfunction number. After that has been done,
58 * the rest of the instruction can be implemented in an ISA-agnostic
59 * manner using the ISA-specific getArguments functions.
60 *
61 * @param func M5 pseudo op major function number (see utility/m5/m5ops.h)
62 * @param subfunc M5 minor function number. Mainly used for annotations.
63 */
64uint64_t pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc);
65
66void arm(ThreadContext *tc);
67void quiesce(ThreadContext *tc);
68void quiesceSkip(ThreadContext *tc);
69void quiesceNs(ThreadContext *tc, uint64_t ns);
70void quiesceCycles(ThreadContext *tc, uint64_t cycles);
71uint64_t quiesceTime(ThreadContext *tc);
72uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
73    uint64_t offset);
74uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
75    uint64_t offset, Addr filenameAddr);
76void loadsymbol(ThreadContext *xc);
77void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
78uint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2);
79uint64_t rpns(ThreadContext *tc);
80void wakeCPU(ThreadContext *tc, uint64_t cpuid);
81void m5exit(ThreadContext *tc, Tick delay);
82void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
83void resetstats(ThreadContext *tc, Tick delay, Tick period);
84void dumpstats(ThreadContext *tc, Tick delay, Tick period);
85void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
86void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
87void debugbreak(ThreadContext *tc);
88void switchcpu(ThreadContext *tc);
89void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
90void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
91void togglesync(ThreadContext *tc);
92
93} // namespace PseudoInst
94
95#endif // __SIM_PSEUDO_INST_HH__
96