12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35224Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45224Sksewell@umich.edu * All rights reserved. 52131SN/A * 65224Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75224Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85224Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95224Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105224Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115224Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125224Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135224Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145224Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155224Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175224Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185224Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195224Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205224Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215224Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225224Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235224Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245224Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255224Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265224Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275224Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295224Sksewell@umich.edu * Authors: Gabe Black 305224Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 328696Sguodeyuan@tsinghua.org.cn * Zhengxing Li 338696Sguodeyuan@tsinghua.org.cn * Deyuan Guo 342131SN/A */ 352131SN/A 362239SN/A#ifndef __MIPS_FAULTS_HH__ 372239SN/A#define __MIPS_FAULTS_HH__ 382131SN/A 398575Sgblack@eecs.umich.edu#include "arch/mips/pra_constants.hh" 408575Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 418575Sgblack@eecs.umich.edu#include "debug/MipsPRA.hh" 422131SN/A#include "sim/faults.hh" 438738Sgblack@eecs.umich.edu#include "sim/full_system.hh" 442447SN/A 452447SN/Anamespace MipsISA 462447SN/A{ 476378Sgblack@eecs.umich.edu 4811294Sandreas.hansson@arm.comtypedef Addr FaultVect; 492131SN/A 508578Sgblack@eecs.umich.eduenum ExcCode { 518578Sgblack@eecs.umich.edu // A dummy value to use when the code isn't defined or doesn't matter. 528578Sgblack@eecs.umich.edu ExcCodeDummy = 0, 538578Sgblack@eecs.umich.edu 548578Sgblack@eecs.umich.edu ExcCodeInt = 0, 558578Sgblack@eecs.umich.edu ExcCodeMod = 1, 568578Sgblack@eecs.umich.edu ExcCodeTlbL = 2, 578578Sgblack@eecs.umich.edu ExcCodeTlbS = 3, 588578Sgblack@eecs.umich.edu ExcCodeAdEL = 4, 598578Sgblack@eecs.umich.edu ExcCodeAdES = 5, 608578Sgblack@eecs.umich.edu ExcCodeIBE = 6, 618578Sgblack@eecs.umich.edu ExcCodeDBE = 7, 628578Sgblack@eecs.umich.edu ExcCodeSys = 8, 638578Sgblack@eecs.umich.edu ExcCodeBp = 9, 648578Sgblack@eecs.umich.edu ExcCodeRI = 10, 658578Sgblack@eecs.umich.edu ExcCodeCpU = 11, 668578Sgblack@eecs.umich.edu ExcCodeOv = 12, 678578Sgblack@eecs.umich.edu ExcCodeTr = 13, 688578Sgblack@eecs.umich.edu ExcCodeC2E = 18, 698578Sgblack@eecs.umich.edu ExcCodeMDMX = 22, 708578Sgblack@eecs.umich.edu ExcCodeWatch = 23, 718578Sgblack@eecs.umich.edu ExcCodeMCheck = 24, 728578Sgblack@eecs.umich.edu ExcCodeThread = 25, 738578Sgblack@eecs.umich.edu ExcCodeCacheErr = 30 748578Sgblack@eecs.umich.edu}; 758578Sgblack@eecs.umich.edu 768566Sgblack@eecs.umich.educlass MipsFaultBase : public FaultBase 772131SN/A{ 782131SN/A public: 798566Sgblack@eecs.umich.edu struct FaultVals 808566Sgblack@eecs.umich.edu { 818566Sgblack@eecs.umich.edu const FaultName name; 828578Sgblack@eecs.umich.edu const FaultVect offset; 838578Sgblack@eecs.umich.edu const ExcCode code; 848566Sgblack@eecs.umich.edu }; 858566Sgblack@eecs.umich.edu 868578Sgblack@eecs.umich.edu void setExceptionState(ThreadContext *, uint8_t); 878578Sgblack@eecs.umich.edu 888578Sgblack@eecs.umich.edu virtual FaultVect offset(ThreadContext *tc) const = 0; 898578Sgblack@eecs.umich.edu virtual ExcCode code() const = 0; 908578Sgblack@eecs.umich.edu virtual FaultVect base(ThreadContext *tc) const 918578Sgblack@eecs.umich.edu { 928578Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 938696Sguodeyuan@tsinghua.org.cn if (!status.bev) 948578Sgblack@eecs.umich.edu return tc->readMiscReg(MISCREG_EBASE); 958578Sgblack@eecs.umich.edu else 968578Sgblack@eecs.umich.edu return 0xbfc00200; 978578Sgblack@eecs.umich.edu } 988578Sgblack@eecs.umich.edu 998578Sgblack@eecs.umich.edu FaultVect 1008578Sgblack@eecs.umich.edu vect(ThreadContext *tc) const 1018578Sgblack@eecs.umich.edu { 1028578Sgblack@eecs.umich.edu return base(tc) + offset(tc); 1038578Sgblack@eecs.umich.edu } 1048578Sgblack@eecs.umich.edu 10510417Sandreas.hansson@arm.com void invoke(ThreadContext * tc, const StaticInstPtr &inst = 10610417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr); 1072131SN/A}; 1082131SN/A 1098566Sgblack@eecs.umich.edutemplate <typename T> 1108566Sgblack@eecs.umich.educlass MipsFault : public MipsFaultBase 1112131SN/A{ 1128566Sgblack@eecs.umich.edu protected: 1138566Sgblack@eecs.umich.edu static FaultVals vals; 1142131SN/A public: 1158566Sgblack@eecs.umich.edu FaultName name() const { return vals.name; } 1168578Sgblack@eecs.umich.edu FaultVect offset(ThreadContext *tc) const { return vals.offset; } 1178578Sgblack@eecs.umich.edu ExcCode code() const { return vals.code; } 1188578Sgblack@eecs.umich.edu}; 1198578Sgblack@eecs.umich.edu 1208578Sgblack@eecs.umich.educlass SystemCallFault : public MipsFault<SystemCallFault> {}; 1218578Sgblack@eecs.umich.educlass ReservedInstructionFault : public MipsFault<ReservedInstructionFault> {}; 1228578Sgblack@eecs.umich.educlass ThreadFault : public MipsFault<ThreadFault> {}; 1238578Sgblack@eecs.umich.educlass IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {}; 1248578Sgblack@eecs.umich.educlass TrapFault : public MipsFault<TrapFault> {}; 1258578Sgblack@eecs.umich.educlass BreakpointFault : public MipsFault<BreakpointFault> {}; 1268578Sgblack@eecs.umich.educlass DspStateDisabledFault : public MipsFault<DspStateDisabledFault> {}; 1278578Sgblack@eecs.umich.edu 1288578Sgblack@eecs.umich.educlass MachineCheckFault : public MipsFault<MachineCheckFault> 1298578Sgblack@eecs.umich.edu{ 1308578Sgblack@eecs.umich.edu public: 1318578Sgblack@eecs.umich.edu bool isMachineCheckFault() { return true; } 1328578Sgblack@eecs.umich.edu}; 1338578Sgblack@eecs.umich.edu 1348578Sgblack@eecs.umich.educlass ResetFault : public MipsFault<ResetFault> 1358578Sgblack@eecs.umich.edu{ 1368578Sgblack@eecs.umich.edu public: 13710417Sandreas.hansson@arm.com void invoke(ThreadContext * tc, const StaticInstPtr &inst = 13810417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr); 1398578Sgblack@eecs.umich.edu 1408578Sgblack@eecs.umich.edu}; 1418578Sgblack@eecs.umich.edu 1428578Sgblack@eecs.umich.educlass SoftResetFault : public MipsFault<SoftResetFault> 1438578Sgblack@eecs.umich.edu{ 1448578Sgblack@eecs.umich.edu public: 14510417Sandreas.hansson@arm.com void invoke(ThreadContext * tc, const StaticInstPtr &inst = 14610417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr); 1478578Sgblack@eecs.umich.edu}; 1488578Sgblack@eecs.umich.edu 1498578Sgblack@eecs.umich.educlass NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt> 1508578Sgblack@eecs.umich.edu{ 1518578Sgblack@eecs.umich.edu public: 15210417Sandreas.hansson@arm.com void invoke(ThreadContext * tc, const StaticInstPtr &inst = 15310417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr); 1548578Sgblack@eecs.umich.edu}; 1558578Sgblack@eecs.umich.edu 1568578Sgblack@eecs.umich.educlass CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault> 1578578Sgblack@eecs.umich.edu{ 1588578Sgblack@eecs.umich.edu protected: 1598578Sgblack@eecs.umich.edu int coProcID; 1608578Sgblack@eecs.umich.edu public: 1618578Sgblack@eecs.umich.edu CoprocessorUnusableFault(int _procid) : coProcID(_procid) 1628578Sgblack@eecs.umich.edu {} 1638578Sgblack@eecs.umich.edu 1648578Sgblack@eecs.umich.edu void 16510417Sandreas.hansson@arm.com invoke(ThreadContext * tc, const StaticInstPtr &inst = 16610417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr) 1678578Sgblack@eecs.umich.edu { 1688578Sgblack@eecs.umich.edu MipsFault<CoprocessorUnusableFault>::invoke(tc, inst); 1698738Sgblack@eecs.umich.edu if (FullSystem) { 1708578Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 1718578Sgblack@eecs.umich.edu cause.ce = coProcID; 1728696Sguodeyuan@tsinghua.org.cn tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 1738578Sgblack@eecs.umich.edu } 1748578Sgblack@eecs.umich.edu } 1758578Sgblack@eecs.umich.edu}; 1768578Sgblack@eecs.umich.edu 1778578Sgblack@eecs.umich.educlass InterruptFault : public MipsFault<InterruptFault> 1788578Sgblack@eecs.umich.edu{ 1798578Sgblack@eecs.umich.edu public: 1808578Sgblack@eecs.umich.edu FaultVect 1818578Sgblack@eecs.umich.edu offset(ThreadContext *tc) const 1828578Sgblack@eecs.umich.edu { 1838578Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 1848696Sguodeyuan@tsinghua.org.cn // offset 0x200 for release 2, 0x180 for release 1. 1858696Sguodeyuan@tsinghua.org.cn return cause.iv ? 0x200 : 0x180; 1868578Sgblack@eecs.umich.edu } 1878566Sgblack@eecs.umich.edu}; 1888566Sgblack@eecs.umich.edu 1898575Sgblack@eecs.umich.edutemplate <typename T> 1908575Sgblack@eecs.umich.educlass AddressFault : public MipsFault<T> 1918575Sgblack@eecs.umich.edu{ 1928575Sgblack@eecs.umich.edu protected: 1938575Sgblack@eecs.umich.edu Addr vaddr; 1948575Sgblack@eecs.umich.edu bool store; 1958575Sgblack@eecs.umich.edu 1968575Sgblack@eecs.umich.edu AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store) 1978575Sgblack@eecs.umich.edu {} 1988578Sgblack@eecs.umich.edu 1998578Sgblack@eecs.umich.edu void 20010417Sandreas.hansson@arm.com invoke(ThreadContext * tc, const StaticInstPtr &inst = 20110417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr) 2028578Sgblack@eecs.umich.edu { 2038578Sgblack@eecs.umich.edu MipsFault<T>::invoke(tc, inst); 2048738Sgblack@eecs.umich.edu if (FullSystem) 2058578Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); 2068578Sgblack@eecs.umich.edu } 2078578Sgblack@eecs.umich.edu}; 2088578Sgblack@eecs.umich.edu 2098578Sgblack@eecs.umich.educlass AddressErrorFault : public AddressFault<AddressErrorFault> 2108578Sgblack@eecs.umich.edu{ 2118578Sgblack@eecs.umich.edu public: 2128578Sgblack@eecs.umich.edu AddressErrorFault(Addr _vaddr, bool _store) : 2138578Sgblack@eecs.umich.edu AddressFault<AddressErrorFault>(_vaddr, _store) 2148578Sgblack@eecs.umich.edu {} 2158578Sgblack@eecs.umich.edu 2168578Sgblack@eecs.umich.edu ExcCode 2178578Sgblack@eecs.umich.edu code() const 2188578Sgblack@eecs.umich.edu { 2198578Sgblack@eecs.umich.edu return store ? ExcCodeAdES : ExcCodeAdEL; 2208578Sgblack@eecs.umich.edu } 2218578Sgblack@eecs.umich.edu 2228575Sgblack@eecs.umich.edu}; 2238575Sgblack@eecs.umich.edu 2248575Sgblack@eecs.umich.edutemplate <typename T> 2258575Sgblack@eecs.umich.educlass TlbFault : public AddressFault<T> 2268575Sgblack@eecs.umich.edu{ 2278575Sgblack@eecs.umich.edu protected: 2288575Sgblack@eecs.umich.edu Addr asid; 2298575Sgblack@eecs.umich.edu Addr vpn; 2308575Sgblack@eecs.umich.edu 2318575Sgblack@eecs.umich.edu TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) : 2328575Sgblack@eecs.umich.edu AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn) 2338575Sgblack@eecs.umich.edu {} 2348575Sgblack@eecs.umich.edu 2358575Sgblack@eecs.umich.edu void 2368575Sgblack@eecs.umich.edu setTlbExceptionState(ThreadContext *tc, uint8_t excCode) 2378575Sgblack@eecs.umich.edu { 2388575Sgblack@eecs.umich.edu this->setExceptionState(tc, excCode); 2398575Sgblack@eecs.umich.edu 2408575Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr); 2418575Sgblack@eecs.umich.edu EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 2428575Sgblack@eecs.umich.edu entryHi.asid = this->asid; 2438575Sgblack@eecs.umich.edu entryHi.vpn2 = this->vpn >> 2; 2448575Sgblack@eecs.umich.edu entryHi.vpn2x = this->vpn & 0x3; 2458575Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 2468575Sgblack@eecs.umich.edu 2478575Sgblack@eecs.umich.edu ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 2488575Sgblack@eecs.umich.edu context.badVPN2 = this->vpn >> 2; 2498575Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 2508575Sgblack@eecs.umich.edu } 2518575Sgblack@eecs.umich.edu 2528578Sgblack@eecs.umich.edu void 25310417Sandreas.hansson@arm.com invoke(ThreadContext * tc, const StaticInstPtr &inst = 25410417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr) 2558578Sgblack@eecs.umich.edu { 2568738Sgblack@eecs.umich.edu if (FullSystem) { 2578696Sguodeyuan@tsinghua.org.cn DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name()); 2588696Sguodeyuan@tsinghua.org.cn Addr vect = this->vect(tc); 2598578Sgblack@eecs.umich.edu setTlbExceptionState(tc, this->code()); 2608696Sguodeyuan@tsinghua.org.cn tc->pcState(vect); 2618578Sgblack@eecs.umich.edu } else { 2628578Sgblack@eecs.umich.edu AddressFault<T>::invoke(tc, inst); 2638578Sgblack@eecs.umich.edu } 2648578Sgblack@eecs.umich.edu } 2655222Sksewell@umich.edu 2668578Sgblack@eecs.umich.edu ExcCode 2678578Sgblack@eecs.umich.edu code() const 2688578Sgblack@eecs.umich.edu { 2698578Sgblack@eecs.umich.edu return this->store ? ExcCodeTlbS : ExcCodeTlbL; 2708578Sgblack@eecs.umich.edu } 2715222Sksewell@umich.edu}; 2725222Sksewell@umich.edu 2738575Sgblack@eecs.umich.educlass TlbRefillFault : public TlbFault<TlbRefillFault> 2745222Sksewell@umich.edu{ 2755222Sksewell@umich.edu public: 2768575Sgblack@eecs.umich.edu TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) : 2778575Sgblack@eecs.umich.edu TlbFault<TlbRefillFault>(asid, vaddr, vpn, store) 2788575Sgblack@eecs.umich.edu {} 2798578Sgblack@eecs.umich.edu 2808578Sgblack@eecs.umich.edu FaultVect 2818578Sgblack@eecs.umich.edu offset(ThreadContext *tc) const 2828578Sgblack@eecs.umich.edu { 2838578Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 2848578Sgblack@eecs.umich.edu return status.exl ? 0x180 : 0x000; 2858578Sgblack@eecs.umich.edu } 2865222Sksewell@umich.edu}; 2876378Sgblack@eecs.umich.edu 2888575Sgblack@eecs.umich.educlass TlbInvalidFault : public TlbFault<TlbInvalidFault> 2895222Sksewell@umich.edu{ 2905222Sksewell@umich.edu public: 2918575Sgblack@eecs.umich.edu TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) : 2928575Sgblack@eecs.umich.edu TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store) 2938575Sgblack@eecs.umich.edu {} 2946378Sgblack@eecs.umich.edu}; 2955222Sksewell@umich.edu 2968575Sgblack@eecs.umich.educlass TlbModifiedFault : public TlbFault<TlbModifiedFault> 2975222Sksewell@umich.edu{ 2985222Sksewell@umich.edu public: 2998575Sgblack@eecs.umich.edu TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) : 3008575Sgblack@eecs.umich.edu TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false) 3018575Sgblack@eecs.umich.edu {} 3025222Sksewell@umich.edu 3038737Skoansin.tan@gmail.com ExcCode code() const { return MipsFault<TlbModifiedFault>::code(); } 3044661Sksewell@umich.edu}; 3054661Sksewell@umich.edu 30612032Sandreas.sandberg@arm.com/* 30712032Sandreas.sandberg@arm.com * Explicitly declare template static member variables to avoid warnings 30812032Sandreas.sandberg@arm.com * in some clang versions 30912032Sandreas.sandberg@arm.com */ 31012032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<SystemCallFault>::vals; 31112032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<ReservedInstructionFault>::vals; 31212032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<ThreadFault>::vals; 31312032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<IntegerOverflowFault>::vals; 31412032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<TrapFault>::vals; 31512032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<BreakpointFault>::vals; 31612032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<DspStateDisabledFault>::vals; 31712032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<MachineCheckFault>::vals; 31812032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<ResetFault>::vals; 31912032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<SoftResetFault>::vals; 32012032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<NonMaskableInterrupt>::vals; 32112032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<CoprocessorUnusableFault>::vals; 32212032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<InterruptFault>::vals; 32312032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<AddressErrorFault>::vals; 32412032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<TlbInvalidFault>::vals; 32512032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<TlbRefillFault>::vals; 32612032Sandreas.sandberg@arm.comtemplate<> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals; 32712032Sandreas.sandberg@arm.com 32812032Sandreas.sandberg@arm.com 32912032Sandreas.sandberg@arm.com 3307811Ssteve.reinhardt@amd.com} // namespace MipsISA 3312131SN/A 3325222Sksewell@umich.edu#endif // __MIPS_FAULTS_HH__ 333